Browsing by Author "Hwang, Wei"

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0.339fJ/bit/search Energy-Efficient TCAM Macro Design in 40nm LP CMOS
(2014)
Huang, Po-Tsang
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Lai, Shu-Lin
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Chuang, Ching-Te
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Hwang, Wei
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Huang, Jason
In this paper, a 256x40 energy-efficient ternary content addressable memory (TCAM) macro is designed and implemented in 40nm low power (LP) CMOS. Due to the thicker gate oxide in LP process, a 16T TCAM cell with p-type comparison circuits is proposed to increase the I-on/I-off difference of the dynamic circuitry. To further improve energy efficiency, don\'t-care-based ripple search-lines/bit-lines are used to reduce both the switching activities and wire capacitance. Moreover, column-based data-aware power control is employed for leakage power reduction and write-ability improvements. The experimental results show a leakage power reduction of 28.9%, a search-line power reduction of 31.74% and an energy efficiency metric of the TCAM macro of 0.339 fJ/bit/search.
0.4V Reconfigurable Near-Threshold TCAM in 28nm High-k Metal-Gate CMOS Process
(2018-01-01)
Chan, Yun-Sheng
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Huang, Po-Tsang
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Wu, Shang-Lin
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Lung, Sheng-Chi
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Wang, Wei-Chang
This paper presents a near-threshold configurable ternary content addressable memory (TCAM) design for energy-constrained neural network or software-defined network (SDN) applications. A TCAM architecture based on foundry-based 6T SRAM mini-array improves area efficiency and minimizes disturbs to enable operation down to 0.4V, and provides configurable lookup tables for users. To minimize dynamic power consumption, hierarchical precharge structure (HPRE) and don't-care based ripple search-line scheme are utilized for decreasing both the switching activities and wire capacitance. Moreover, power-gating technique, self-timed control and V-trip-tracking write-assist are used to reduce standby power, speed-up propagation delays of global signals and improve write-ability at low voltage, respectively. A reconfigurable TCAM is implemented using UMC 28nm high-k metal gate (HKMG) CMOS process. The design achieves operating frequency of 240MHz (20MHz) with energy consumption of 1.146 (0.621) fJ/bit/search at 0.9V (0.4V).
2-l.evel FIFO architecture design for switch fabrics in network-on-chip
(2006)
Huang, Po-Tsang
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Hwang, Wei
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The network-on-chip (NoC) architecture provides the integrated solution for system-on-chip (SoC) design. The buffer architecture and sizes, however, dominate the performance of NoC and influence on the design of arbiters in the switch fabrics. The 2-level FIFO architecture is proposed. It simplifies the design of the arbitration algorithm and gets better performance than other buffer architectures without increasing the buffer sizes. The concept of the shared memory mechanism and multiple accesses for the buffers are developed. The FIFO architecture is implemented and simulated with TSMC 0.13um CMOS technology by HSPICE and Verilog. The operation frequency of the 2-level FIFO reaches 400MHz.
2.5D Heterogeneously Integrated Bio-Sensing Microsystem for Multi-Channel Neural-Sensing Applications
(2014-01-01)
Huang, Po-Tsang
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Chou, Lei-Chun
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Huang, Teng-Chieh
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Wu, Shang-Lin
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Wang, Tang-Shuan
2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications
(2014-12-01)
Huang, Po-Tsang
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Wu, Shang-Lin
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Huang, Yu-Chieh
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Chou, Lei-Chun
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Huang, Teng-Chieh
Heterogeneously integrated and miniaturized neural sensing microsystems are crucial for brain function investigation. In this paper, a 2.5D heterogeneously integrated bio-sensing microsystem with mu-probes and embedded through-silicon-via (TSVs) is presented for high-density neural sensing applications. This microsystem is composed of mu-probes with embedded TSVs, 4 dies and a silicon interposer. For capturing 16-channel neural signals, a 24 x 24 mu-probe array with embedded TSVs is fabricated on a 5 x 5 mm2 chip and bonded on the back side of the interposer. Thus, each channel contains 6 x 6 mu-probes with embedded TSVs. Additionally, the 4 dies are bonded on the front side of the interposer and designed for biopotential acquisition, feature extraction and classification via low-power analog front-end (AFE) circuits, area-power-efficient analog-to-digital converters (ADCs), configurable discrete wavelet transforms (DWTs), filters, and a MCU. An on-interposer bus (mu-SPI) is designed for transferring data on the interposer. Finally, the successful in-vivo test demonstrated the proposed 2.5D heterogeneously integrated bio-sensing microsystem. The overall power of this microsystem is only 676.3 mu W for 16-channel neural sensing.
28nm Near/Sub-Threshold Dual-Port FIFO Memory for Shared Queues in Multi-Sensor Applications
(2018-01-01)
Wu, Yi-Chun
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Huang, Po-Tsang
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Wu, Shang-Lin
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Lung, Sheng-Chi
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Wang, Wei-Chang
For an energy-limited multi-sensing platform, ultra-low-power queueing design is one of the critical challenge to store low-speed sensing data with various sampling frequencies. In this paper, a near/sub-threshold dual-port first-in-first-out (FIFO) memory is proposed for shared queues in a unified queuing architecture. This ultra-lowpower FIFO memory is designed and implemented using bitinterleaved 12T near-/sub-threshold dual-port SRAM bit-cells, write/read-assist circuitries, and adaptive timing tracking circuits. The 12T bit-cell eliminates both read and write half-select disturbance. Additionally, an adaptive timing tracing circuitry and negative bit-line circuits are employed to against PVT variation and to enhance write ability, respectively. Furthermore, the self-timed pointers and short ripple bit-lines are designed to avoid global long metal lines with large loading. A 256x16 dual-port FIFO memory is implemented in UMC 28nm HKMG CMOS technology. This FIFO memory can be operated at 0.4V with 10MHz for read operations. Moreover, up to 60% power reduction can be achieved based on the proposed design techniques.
28nm Ultra-Low Power Near-/Sub- threshold First-In-First-Out (FIFO) Memory for Multi-Bio-Signal Sensing Platforms
(2016)
Hsu, Wei-Shen
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Huang, Po-Tsang
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Wu, Shang-Lin
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Chuang, Ching-Te
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Hwang, Wei
In this paper, an ultra-low-power near-/sub-threshold first-in-firstout (FIFO) memory is proposed for energy-constrained bio-signal sensing applications. This FIFO memory is designed and implemented using folded bit-interleaved 10T near-/sub-threshold SRAM bit-cells, self-timed pointers and bank-level power control circuits. The 10T SRAM cell is proposed for the bit-interleaving structure with 2.4X write static noise margin (SNM) improvement. The folded bit-interleaving structure reduces the bit-line capacitance and avoids long routing wires for the circular self-timed pointers. Additionally, the event-driven self-timed pointers are designed to reduce the power consumption of clock buffers. For further decreasing the overall power dissipation, bank-level column-based power control circuitry is proposed to switch the voltages for different banks to achieve 60.5% power saving. A 512x16 FIFO memory is implemented in UMC 28nm HKMG CMOS technology. Compared with the prior arts, 47X power reduction and 2.7X area efficiency can be achieved by the proposed design techniques.
A 0.33-V, 500-kHz, 3.94-mu W 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist
(2012-12-01)
Lu, Chien-Yu
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Tu, Ming-Hsien
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Yang, Hao-I
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Wu, Ya-Ping
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Huang, Huan-Shun
This paper presents an ultra-low-power 72-Kb 9T static random-access memory (SRAM) with a ripple bit-line (RPBL) structure and negative bit-line (NBL) write-assist. The RPBL scheme provides over 40% read access performance improvement for VDD below 0.4 V compared with the conventional hierarchical bit-line structure. A variation-tolerant ripple-initiated NBL write-assist scheme with the transient negative pulse coupled only into the single selected local bit-line segment is employed to enhance the NBL, boosting efficiency and reducing power consumption. The 331 x 385 mu m(2) 72-Kb SRAM macro has been fabricated in UMC 40-nm low-power CMOS technology and was tested with full suites of SRAM compiler qualification patterns. Error-free full functionality without redundancy is achieved from 1.5 V down to 0.33 V. The measured maximum operation frequency is 220 MHz (500 kHz) at 1.1 V (0.33 V) and 25 degrees C. The measured total power consumption is 3.94 mu W at 0.33 V, 500 kHz, and 25 degrees C.
A 0.42V Vccmin ASIC-Compatible Pulse-Latch Solution as a Replacement for a Traditional Master-Slave Flip-Flop in a Digital SOC
(2014)
Dhong, Sang
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Guo, Richard
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Kuo, Ming-Zhang
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Yang, Ping-Lin
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Lin, Cheng-Chung
We present a pulse latch with a measured Vccmin at the circuit of 0.42 V and pulse width of approximately 3 FO4-inverter delays. A wider operating window and reduced dependence on the input rise-time and PVT variations were obtained using a new pulse generator. A pulse in the new generator starts when its input crosses the switching level of its input gate, unlike in the classic text-book-style pulse-generator. An 8 to 10% improvement in power, performance, and area (PPA) of a typical digital SOC is observed when a group of pulse latches is driven by a distributed clock regenerator (OCR). The OCR has the new pulse generator at its input stage and provides pulse clocks to the pulse latches. Experimental results in a 28-nm HKMG process closely match SPICE simulations.
A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist
(2017-07-01)
Wu, Shang-Lin
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Li, Kuang-Yu
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Huang, Po-Tsang
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Hwang, Wei
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Tu, Ming-Hsien
This paper presents a 28-nm 256-kb 6T static random access memory operating down to near-threshold regime. The cell array is built on foundry 4-by-2 mini-array with split single-ended large signal sensing to enable an ultra-short local bit-line of 4-b length to improve variation tolerance and performance, and to reduce disturb while maintaining manufacturability. The design employs threshold power gating to facilitate lower NAP (Sleep) mode voltage/power and faster wake-up for the cell array, and low-swing global read bit-line (GRBL) with integrated low-swing voltage precharger to improve read performance and reduce the dynamic read power. A cell Vtrip-tracking write-assist (VTWA) lowers the selected sub-array supply to cell inverter trip voltage to enhance write-ability while providing PVT tracking capability to ensure adequate data retention margin for unselected cells in the selected sub-array. The 256-kb test chip is implemented in UMC 28-nm high-kappa metal-gate (H kappa MG) CMOS technology with macro area of 1058.22 x 374.76 mu m(2). Error-free full functionality is achieved from 0.9 down to 0.5 V (limited by read VMIN) without redundancy. The low-swing GRBL reduces dynamic power by 6.5% (8.0%) at 0.9 V (0.6 V). The VTWA improves the write VMIN by 75 mV (from 0.525 to 0.45 V). The measured maximum operation frequency is 735 MHz (20 MHz) at 0.9 V (0.5 V), TT corner, 25(omicron).
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
(2006)
Chao, Tzu-Chiang
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Hwang, Wei
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, a new architecture and algorithm for all digital phase-locked loop (ADPLL) is proposed. By using the new search algorithm, it can accomplish phase lock process within 18 input clock cycles. By using the new architecture, we can combine the functions of the frequency comparator, phase detector and gain generator in one hard block. Also, a new digitally controlled oscillator (DCO) structure for low power, small area is presented and its frequency range is from 200 MHz to 750 MHz with a supply voltage 1.2v. The total power consumption of ADPLL is 1.7mW. This ADPLL has characteristics of fast frequency locking, small hard cost and lower power consumption. This ADPLL is designed and implemented by TSMC's 0.13um CMOS technology.
A 1.9mW portable ADPLL-based frequency synthesizer for high speed clock generation
(2007)
Chang, Ming-Hung
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Yang, Zong-Xi
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Hwang, Wei
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電子與資訊研究中心
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Microelectronics and Information Systems Research Center
An ADPLL-based frequency synthesizer has been designed and implemented with TSMC 130nm technology model. The cores of it are digital controlled oscillator (DCO) and phase frequency detector (PFD). A modified digitally controlled delay element (DCDE) with characteristics of its monotonicity and insensitivity to PVT variations is presented for the DCO design. A new PFD architecture that can finish phase and frequency comparison and adjustment in one reference cycle is presented. This frequency synthesizer can operate from 300MHz to 1GHz, and achieve frequency acquisition in fifteen reference clock cycles (worst case scenario). The peak-to-peak jitter of the output clock is less than 120ps at 300MRz. Furthermore, the design has been ported to TSMC 100nm process as a reusable IP block verification. The total power dissipation of the ADPLL-based frequency synthesizer is 1.9mW (TSMC 100nm technology) at 1GHz with a 1.2V power supply. With such specifications, it is suitable for high speed clock generation in system-on-a-chip (SoC) applications.
A 16kB Tile-able SRAM Macro Prototype for an Operating Window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS
(2014)
Kuo, Ming-Zhang
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Hsieh, Henry
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Dhong, Sang
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Yang, Ping-Lin
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Lin, Cheng-Chung
This paper describes a tile-able 16-kByte 6-T SRAM macro in a High-K Metal-Gate (HKMG) 28-nm bulk technology with an operating window from 4.8 GHz at 1.12 V VDD down to 10 MHz at 0.5V, meeting almost all of the Dynamic Voltage Frequency Scaling (DVFS) requirements of Level-1 (L1) caches of a digital microprocessor SOC. It uses an unmodified technology-supported 0.156um(2) high-current (HC) SRAM cell. Innovative and carefully optimized circuit solutions provide the wide operating range measured in hardware. We also discuss two circuit improvements, a cross-coupled PMOS-pair for each bitline-pair with mux readout and an independently-controlled precharge-and-write driver (ICPW), which gives a wider DVFS operating window with reduced sensitivities to Process-Voltage-Temperature (PVT) variations. Improved SRAM macros with new circuits have been designed and laid out and their performance and area verified in simulation.
A 2.1-mu W 0.3V-1.0V Wide Locking Range Multiphase DLL Using Self-Estimated SAR Algorithm
(2009)
Chang, Yi-Ming
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Chang, Ming-Hung
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Hwang, Wei
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents an all-digital multiphase delay-locked loop (ADMDLL) for wide-locking range and micro-power applications. To enhance locking range of the ADMDLL, we proposed the self-estimated successive approximation register-controlled (SESAR) algorithm, which uses the frequency-estimation selector (FES) to avoid harmonic lock issue. In addition, the FES can reuse the delay line to reduce circuit area and power dissipation significantly. By using the stack effect, the proposed leakage-reduced delay unit can save 12% leakage power consumption. After locking, the dynamic frequency monitor window is proposed to compensation phase error caused by PVT variations. The proposed ADMDLL is capable of operating in wide supply voltage range from 0.3V to 1.0V. The power dissipation is only 520 mu W at 1.25GHz/1.0V, and 2.1 mu W at 13MHz/0.3V, respectively. This work is based on UMC 90nm standard CMOS technology.
A 256x128 energy-efficient TCAM with novel low power schemes
(2007)
Huang, Po-Tsang
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Chang, Shu-Wei
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Liu, Wen-Yen
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Hwang, Wei
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電子工程學系及電子研究所
Novel low power schemes for energy-efficient ternary content-addressable memory (TCAM) are presented in this paper. The butterfly match-line scheme is based on the pseudo-footless clock-data pre-charged architecture. It connects each pipelined stage in a butterfly style which significantly decreases both search time and power consumption. For applications like IP-address forwarding in a network router, a new don't-care based power gating and don't-care based hierarchical (DCBH) search-line scheme are proposed. The search-line is divided into global search-line (GSL) and local search-line (LSL) which is controlled by don't-care state in DCBH search-line scheme. Therefore, the power consumption on search line is reduced without any search time overhead. Besides, the power saving of the standby power is achieved by power gating technique. The proposed 256 x 128bit TCAM has been implemented with TSMC 0.13um CMOS technology. It shows 0.55ns of match evaluation time on search operation with 0.29 fJ/bit/search of energy efficiency.
A 300-mV 36-mu W Multiphase Dual Digital Clock Output Generator with Self-Calibration
(2008)
Chang, Ming-Hung
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Chuang, Li-Pu
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Chang, I-Ming
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Hwang, Wei
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電子工程學系及電子研究所
A 300mV 20MHz-35OMHz low variation all-digital multiphase dual clock output generator with rapid self-calibration has been designed with UMC 90nm CMOS technology model. The PVT immunity properties of several classic delay elements in low voltage era have been studied. A low voltage calibration unit is also proposed to reduce the maximum multiphase error no larger than 120ps when delay-locked loop is operating at 40MHz/300mV. A novel static current-mirror-based phase blender is developed to provide wide range accurate twice multiphase information, and phase error is reduced by no more than 11.83%. The clock generator could provide more independent outputs by simply using additional edge combiner. The frequency and phase of output clock could be dynamically adjusted without relocking process. The total power dissipation of the all-digital multiphase dual digital clock output generator is 36 mu W at 40MHz/300mV.
A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist
(2014-12-01)
Lien, Nan-Chun
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Chu, Li-Wei
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Chen, Chien-Hen
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Yang, Hao-I.
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Tu, Ming-Hsien
This paper presents a cross-point 512 kb 8 T pipeline static random-access memory (SRAM). The cross-point structure eliminates write half-select disturb to facilitate bit-interleaving architecture for enhanced soft error immunity. The design employs boosted word-line (WL) for improving both read performance and write-ability. A ripple bit-line (RiBL) structure provides 30%-44% read access performance improvement and 2x-3.5x variation immunity at 0.7 V compared with the conventional hierarchical bit-line (HiBL) schemes. An adaptive data-aware write-assist (ADAWA) with VCS tracking is employed to further enhance the write-ability while ensuring adequate stability for half-selected cells on the selected bit-lines. An adaptive voltage detector (AVD) with binary boosting control is used to mitigating gate electric over-stress. The design is implemented in UMC 40 nm low-power (40LP) CMOS technology. The 512 kb test chip operates from 1.5 V to 0.65 V, with maximum operation frequency of 800 MHz@1.1 V and 200 MHz@0.65 V. The measured power consumption is 0.5 mW/MHz (active) and 4.4 mW (standby) at 1.1 V, and 0.107 mW/MHz (active) and 0.367 mW (standby) at 0.65 V.
A 40nm 1.0Mb 6T Pipeline SRAM with Digital-Based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS Tracking and Adaptive Voltage Detector for Boosting Control
(2013-01-01)
Liao, Wei-Nan
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Lien, Nan-Chun
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Chang, Chi-Shin
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Chu, Li-Wei
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Yang, Hao-I
This paper presents a 40nm 1.0Mb pipeline 6T SRAM featuring digital-based Bit-Line Under-Drive (BLUD) with large-signal sensing and Three-Step-Up Word-Line (TSUWL) to improve RSNM, Read performance and Write-ability. An Adaptive DataAware Write-Assist (ADAWA) with VCS tracking is employed to further improve Write-ability while ensuring adequate stability for half-selected cells on the selected bit-lines. An Adaptive Voltage Detector (AVD) with binary boosting control is used to mitigate gate dielectric over-stress. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of 1.07GHz@1.2V and 887MHz@1.1V at 25 degrees C. The measured power consumption is 43.47mW (Active)/3.91mW (Leakage) at 1.1V and 8.97mW (Active)/0.52mW (Leakage) at 0.7V, TT, 25 degrees C.
A 40nm 1.0Mb Pipeline 6T SRAM with Variation-Tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist
(2013)
Chang, Chi-Shin
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Yang, Hao-I
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Liao, Wei-Nan
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Lin, Yi-Wei
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Lien, Nan-Chun
We present a 1.0Mb pipeline 6T SRAM in 40nm Low-Power CMOS technology. The design employs a variation-tolerant Step-Up Word-Line (SUWL) to improve the Read Static Noise Margin (RSNM) without compromising the Read performance and Write-ability. The Write-ability is further enhanced by an Adaptive Data-Aware Write-Assist (ADAWA) scheme. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of 800MHz@1.2V and 25 degrees C. The measured power consumption is 23.21mW (Active)/2.42mW (Leakage) at 1.2V, TT, 25 degrees C; and 6.01mW (Active)/0.35mW (Leakage) at 0.7V, TT, 25 degrees C.
A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop
(2008)
Chuang, Li-Pu
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Chang, Ming-Hung
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Huang, Po-Tsang
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Kan, Chih-Hao
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Hwang, Wei
A 333MHz-1GHz all-digital multiphase delay-locked loop with precise multi-phase output has been designed with TSMC 130nm CMOS technology model. A modified binary search algorithm is proposed to match up a linear approximate delay element (LADE). The LADE property of linearity and insensitive to PVT variations is good for digitally-controlled delay element. The lock-in time could be reduced down to 14 reference clock cycles, and enhance the operation range based on LADE[binary search algorithm co-operate effort. The timing error caused by process mismatch is further reduced by proposed rapid self-calibration (RSC) algorithm. A calibration unit is designed based on RSC algorithm, which reduces the maximum timing error to less than 9ps when DLL is operating at 500MHz. The entire calibration unit could be turned off after calibration procedure is complete to reduce power consumption. The total power dissipation of the all-digital self-calibrated multiphase delay-locked loop is 5.2mW at 1GHz with a 1.2V power supply.