Browsing by Author "Iwai, Hiroshi"

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A 60-nm-thick enhancement mode In0.65Ga0.35As/InAs/In0.65Ga0.35As high-electron-mobility transistor fabricated using Au/Pt/Ti non-annealed ohmic technology for low-power logic applications
(2016-02)
Fatah, Faiz Aizad
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Lin, Yueh-Chin
;
Liu, Ren-Xuan
;
Yang, Kai-Chun
;
Lin, Tai-We
A 60-nm-thick E-mode In0.65Ga0.35As/InAs/In0.65Ga0.35As high-electron-mobility transistor (HEMT) was successfully fabricated and evaluated by using Au/Pt/Ti-based non-annealed ohmic technology for high-speed and low-power logic applications. The device exhibited a minimal SS of 69mV/decade, a lower DIBL of 30mV/V, an ION/IOFF ratio above 1.2 x 10(4) at V-DS = 0.5V and a high f(T) of 378GHz and f(max) of 214GHz at V-DS = 1.0V. These results demonstrate that non-annealed ohmic contacts can be used for fabricating E-mode In0.65Ga0.35As/InAs/In0.65Ga0.35As HEMTs with excellent electrical characteristics. The fabricated HEMTs are likely to find use in future high-speed and low-power logic applications. (C) 2016 The Japan Society of Applied Physics.
Demonstrating 1 nm-oxide-equivalent-thickness La2O3 and HfO2 multi-layer composite oxides on In0.53Ga0.47As MOS capacitor
(2016-01-08)
Wu, Wen-Hao
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Lin, Yueh-Chin
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Hou, Tzu-Ching
;
Lin, Tai-Wei
;
Hsu, Hisang-Hua
The use of a high k composite dielectric composed of La2O3 and HfO2 layers as the gate dielectric for In0.53Ga0.47As MOS application is proposed. Two multi-layer structures of La2O3 (1 nm)/HfO2 (1 nm) and La2O3 (0.5 nm)/HfO2 (0.5 nm) were deposited and annealed at 450 and 500 degrees C for device performance comparison. X-ray photoelectron spectroscopy, TEM and C-V measurements were used for the interface analysis between the oxide and the semiconductor. Finally, a 1 nm equivalent-oxide-thickness dielectric with small hysteresis of 88 mV and D-it of 1.9 x 10(12) cm(-2) eV(-1) was achieved for six layers of an La2O3 (0.5 nm)/HfO2 (0.5 nm) composite oxide structure on an In0.53Ga0.47As MOS capacitor with a post-deposition annealing temperature of 450 degrees C.
Effect of Postdeposition Annealing Temperatures on Electrical Characteristics of Molecular-Beam-Deposited HfO2 on n-InAs/InGaAs Metal-Oxide-Semiconductor Capacitors
(2012-02-01)
Trinh, Hai-Dang
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Lin, Yueh-Chin
;
Wang, Huan-Chung
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Chang, Chia-Hua
;
Kakushima, Kuniyuki
The electrical characteristics of molecular-beam-deposited HfO2/n-InAs/InGaAs metal-oxide-semiconductor capacitors with different postdeposition annealing (PDA) temperatures (400-550 degrees C) are investigated. Results show that the sample with the PDA temperature of 500 degrees C exhibits the best capacitance-voltage (C-V) behavior with small frequency dispersion and small hysteresis. The X-ray photoelectron spectroscopy (XPS) spectra show the reduction of the amount of As-related oxides to below the XPS detection level when the PDA temperature is up to 500 degrees C. As the PDA temperature was increased to above 500 degrees C, As and In atoms seem to diffuse significantly into HfO2, resulting in the degradation of C-V behavior. (C) 2012 The Japan Society of Applied Physics
Effects of layer sequence and postdeposition annealing temperature on performance of La2O3 and HfO2 multilayer composite oxides on In0.53Ga0.47As for MOS capacitor application
(2014-03-01)
Wu, Wen-Hao
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Lin, Yueh-Chin
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Chuang, Ting-Wei
;
Chen, Yu-Chen
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Hou, Tzu-Ching
In this paper, we report on high-k composite oxides that are formed by depositing multiple layers of HfO2 and La2O3 on In0.53Ga0.47As for MOS device application. Both multilayer HfO2 (0.8 nm)/La2O3 (0.8 nm)/In0.53Ga0.47As and La2O3 (0.8 nm)/HfO2 (0.8 nm)/In0.53Ga0.47As MOS structures were investigated. The effects of oxide thickness and postdeposition annealing (PDA) temperature on the interface properties of the composite oxide MOS capacitors were studied. It was found that a low CET of 1.41 nm at 1 kHz was achieved using three-layer composite oxides. On the other hand, a small frequency dispersion of 2.8% and an excellent D-It of 7.0 Chi 10(11)cm(-2).eV(-1) can be achieved using multiple layers of La2O3 (0.8 nm) and HfO2 (0.8 nm) on the In0.53Ga0.47As MOS capacitor with optimum thermal treatment and layer thickness. (C) 2014 The Japan Society of Applied Physics
Electrical Characterization and Materials Stability Analysis of La2O3/HfO2 Composite Oxides on n-In0.53Ga0.47As MOS Capacitors With Different Annealing Temperatures
(2013-10-01)
Lin, Yueh Chin
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Trinh, Hai Dang
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Chuang, Ting Wei
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Iwai, Hiroshi
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Kakushima, Kuniyuki
In this letter, a high-k composite oxide composed of La2O3 and HfO2 is investigated for n-In0.53Ga0.47As metal-oxide-semiconductor (MOS) capacitor application. The composite oxide was formed by depositing five layers of La2O3 (0.8 nm)/HfO2(0.8 nm) on InGaAs with post deposition annealing at 500 degrees C. The MOS capacitors fabricated show good inversion behavior, high capacitance, low leakage current, with excellent interface trap density (D-it) of 7.0 x 10(11) cm(-2)eV(-1), small hysteresis of 200 mV and low capacitance equivalent thickness of 2.2 nm at 1 kHz were also achieved.
End of the downsizing and world after that
(2016)
Iwai, Hiroshi
;
交大名義發表
;
National Chiao Tung University
The progress of the electronics has been conducted by the downsizing of electron devices for more than 100 years since its beginning in early 20th century. However, it is believed now that the downsizing will reach its limit within a few to several years because of several sure reasons. After reaching the limit there is no Moore\'s law, and we cannot expect such a tremendous progress in cost, performance and energy consumption as we experienced in the past. Although the market for CMOS devices will still keep increasing for future, the technology development will spread to large spectrum of different devices, such as sensor, memory, power, photovoltaic, battery, MEMS devices which are demanded for the coming IoT environment, where everything is connected with internet. This will become a virtual extension of Moore\'s law, and will cause a big paradigm change in a system and society level. In a long term, however, the system fabricated on the solid-state devices and there network cannot compete with the existing bio system in efficiency, and the technology how to use the bio system, and combine the electron and bio system will become important.
End of the Downsizing and World after That
(2017-01-01)
Iwai, Hiroshi
;
交大名義發表
;
National Chiao Tung University
The progress of the electronics has been conducted by the downsizing of electron devices for more than 100 years since its beginning in early 20th century. However, it is believed now that the downsizing will reach its limit within several years because of several sure reasons. After reaching the limit there is no Moore's law, and we cannot expect such a tremendous progress in cost, performance and energy consumption as we experienced in the past. Although the market for CMOS devices will still keep increasing for future, the technology development will spread to large spectrum of different devices, such as sensor, memory, power, photovoltaic, battery, MEMS devices which are demanded for the coming IoT environment, where everything is connected with internet. This will become a virtual extension of Moore's law, and will cause a big paradigm change in a system and society level. In a long term, however, even with the tremendous progress of AI technologies, the system fabricated on the solid-state devices and their network cannot compete with the existing bio system constructed on organic system, in efficiency and maintenance. Thus, the technology how to use the bio system better, or how to combine electron and bio systems better will become very important.
End of the scaling theory and Moore\'s law
(2016)
Iwai, Hiroshi
;
交大名義發表
;
National Chiao Tung University
The progress of the electronics has been conducted until today by the downsizing of devices for more than 100 year since its beginning in early 20th century. However, it is believed now that the downsizing will reach its limit in several years because of several sure reasons. After reaching the limit, we cannot expect such a big progress as the past for electron devices in terms of cost, performance and energy consumption. Then, the effort will be focused to develop various kind of electron devices such as new memory, sensors, power, photovoltaic, battery and MEMS devices which are demanded for IoT era. In a long term, our research and development will shift to how to use the existing bio system more efficiently rather than developing only solid-state devices only.
Enhancement-Mode GaN MIS-HEMTs With LaHfOx Gate Insulator for Power Application
(2017-08-01)
Lin, Yueh Chin
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Huang, Yu Xiang
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Huang, Gung Ning
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Wu, Chia Hsun
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Yao, Jing Neng
This letter reports an E-mode GaN MIS-HEMT using a composite La2O3/HfO2 gate insulator for power device applications. The composite dielectric formed an amorphous LaHfOx layer after post-deposition annealing. The GaN MIS-HEMT with amorphous LaHfOx gate dielectric showed good oxide film quality and excellent HfLaOx/GaN interface properties, as demonstrated by the measured C-V characteristics. Consequently, the E-mode MIS-HEMT was determined to show good V-th stability with only a slight increase in the dynamic R-on after high drain bias stress.
High-permitivity cerium oxide prepared by molecular beam deposition as gate dielectric and passivation layer and applied to AlGaN/GaN power high electron mobility transistor devices
(2016-05)
Chiu, Yu Sheng
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Liao, Jen Ting
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Lin, Yueh Chin
;
Liu, Shin Chien
;
Lin, Tai Ming
High-kappa cerium oxide (CeO2) was applied to AlGaN/GaN high-electron-mobility transistors (HEMTs) as a gate insulator and a passivation layer by molecular beam deposition (MBD) for high-power applications. From capacitance-voltage (C-V) measurement results, the dielectric constant of the CeO2 film was 25.2. The C-V curves showed clear accumulation and depletion behaviors with a small hysteresis (20 mV). Moreover, the interface trap density (D-it) was calculated to be 5.5 x 10(11) eV(-1)cm(-2) at 150 degrees C. A CeO2 MOS-HEMT was fabricated and demonstrated a low subthreshold swing (SS) of 87 mV/decade, a high ON/OFF drain current ratio (I-ON/I-OFF) of 1.14 X 10(9), and a low gate leakage current density (J(leakage)) of 2.85 X 10(-9)Acm(-2) with an improved dynamic ON-resistance (R-ON), which is about one order of magnitude lower than that of a conventional HEMT. (C) 2016 The Japan Society of Applied Physics
Improved linearity and reliability in GaN metal-oxide-semiconductor high-electron-mobility transistors using nanolaminate La2O3/SiO2 gate dielectric
(2016-04)
Hsu, Ching-Hsiang
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Shih, Wang-Cheng
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Lin, Yueh-Chin
;
Hsu, Heng-Tung
;
Hsu, Hisang-Hua
Improved device performance to enable high-linearity power applications has been discussed in this study. We have compared the La2O3/SiO2 AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with other La2O3-based (La2O3/HfO2, La2O3/CeO2 and single La2O3) MOS-HEMTs. It was found that forming lanthanum silicate films can not only improve the dielectric quality but also can improve the device characteristics. The improved gate insulation, reliability, and linearity of the 8 nm La2O3/SiO2 MOS-HEMT were demonstrated. (C) 2016 The Japan Society of Applied Physics
Improved linearity and reliability in GaN metal-oxide-semiconductor high-electron-mobility transistors using nanolaminate La2O3/SiO2 gate dielectric
(2016-04-01)
Hsu, Ching-Hsiang
;
Shih, Wang-Cheng
;
Lin, Yueh-Chin
;
Hsu, Heng-Tung
;
Hsu, Hisang-Hua
Improved device performance to enable high-linearity power applications has been discussed in this study. We have compared the La2O3/SiO2 AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with other La2O3-based (La2O3/HfO2, La2O3/CeO2 and single La2O3) MOS-HEMTs. It was found that forming lanthanum silicate films can not only improve the dielectric quality but also can improve the device characteristics. The improved gate insulation, reliability, and linearity of the 8 nm La2O3/SiO2 MOS-HEMT were demonstrated. (C) 2016 The Japan Society of Applied Physics
Reliability improvement in GaN HEMT power device using a field plate approach
(2017-07-01)
Wu, Wen-Hao
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Lin, Yueh-Chin
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Chin, Ping-Chieh
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Hsu, Chia-Chieh
;
Lee, Jin-Hwa
This study investigates the effect of implementing a field plate on a GaN high-electron-mobility transistor (HEMT) to improve power device reliability. The results indicate that the field plate structure reduces the peak electrical field and interface traps in the device, resulting in higher breakdown voltage, lower leakage current, smaller current collapse, and better threshold voltage control. Furthermore, after high voltage stress, steady dynamic on-resistance and gate capacitance degradation improvement were observed for the device with the field plate. This demonstrates that GaN device reliability can be improved by using the field plate approach. (C) 2017 Elsevier Ltd. All rights reserved.
Study of E-Mode AlGaN/GaN MIS-HEMT with La-silicate Gate Insulator for Power Applications
(2020-02-01)
Huang, Kuan Ning
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Lin, Yueh-Chin
;
Lin, Jia-Ching
;
Hsu, Chia Chieh
;
Lee, Jin Hwa
An enhancement-mode (E-mode) AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) with La2O3/SiO2 gate insulator is investigated for high power application. The La2O3/SiO2 composite oxide formed amorphous La-silicate after post deposition annealing. Good oxide film quality and excellent La-silicate/AlGaN interface properties were achieved as evidenced by the capacitance-voltage (C-V) curves and hysteresis effect of the La-silicate on AlGaN/GaN metal-oxide-semiconductor capacitors. As a result, the E-mode AlGaN/GaN MIS-HEMT with La-silicate gate insulator shows good threshold voltage (V-th) stability and demonstrated only slightly increase in the dynamic on-resistance (R-on) after high drain bias stress test. The device also exhibits high current density of 752 mA/mm, high maximum transconductance of 210 mS/mm, low subthreshold swing of 104 mV/decade, and I-ON/I-OFF = 10(7) when tested at V-DS = 10 V. Furthermore, low on-resistance of 7.6 omega mm, high breakdown voltage of 670 V, and excellent delay time of 4.2 ps were achieved, demonstrating the La-silicate MIS-HEMTs have the potential to be used for power electronic applications.
Study of La2O3/HfO2 Gate Dielectric for n-InAs Metal-Oxide-Semiconductor Capacitor
(2011)
Lin, Yueh-Chin
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Chang, Chia-Hua
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Kakushima, Kuniyuki
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Iwai, Hiroshi
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Shie, Tin-En
In this study, we investigate the composite La2O3/HfO2 high k dielectric as the gate oxide for n-InAs metal-oxide semiconductor (MOS) capacitor. The La2O3 was used for its high k value and HfO2 was used as the diffusion barrier and was deposited between La2O3 and InGaAs to prevent the Inter-diffusion between InAs and La(2)OZ(3) layers after post deposition annealing (PDA). Finally, we demonstrate the La2O3/HfO2 composite oxide structure as the high K dielectric for n-InAs MOS capacitor with enhanced capacitance for the MOS capacitor.