Browsing by Author "JOU, IC"

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A CMOS CURRENT-MODE DESIGN OF MODIFIED LEARNING-VECTOR-QUANTIZATION NEURAL NETWORKS
(1995-09-01)
LIU, RY
;
WU, CY
;
JOU, IC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A modification of LVQ model, Modified LVQ (MLVQ) model, is proposed for the estimation of centroid in pattern recognition. Computer simulation results are presented which demonstrate the behavior of the MLVQ model in estimating the class centroid by utilizing the distance-dependent step size. The results indicate the high potential of less dependence on the initial point as well as the precise settlement of the weight vectors to the centroids. The main feature is that the proposed model is robust to the noise perturbation between two pattern distributions in practical applications. To take advantage of this MLVQ model with the faster training and recalling process for patterns, a hybrid analog-digital processing system is designed by the CMOS current-mode integrated circuit (IC) technology and offers the best attributes of both analog and digital computation. This hybrid processing system operates at microsecond time scale, which enables it to produce real time solutions for complex spatiotemporal problems found in high speed signal processing applications. The overall neural processing system has also been simulated and verified by the HSPICE circuit simulator.
CMOS CURRENT-MODE IMPLEMENTATION OF SPATIOTEMPORAL PROBABILISTIC NEURAL NETWORKS FOR SPEECH RECOGNITION
(1995-06-01)
WU, CY
;
LIU, RY
;
JOU, IC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a Spatiotemporal Probabilistic Neural Network (SPNN) is proposed for spatiotemporal pattern recognition. This new model is developed by applying the concept of Gaussian density function to the network structure of the SPR (SPatiotemporal Pattern Recognition). The main advantages of this model include faster training and recalling process for patterns. In addition, the overall architecture is also simple, modular, regular, locally connected, and suitable for VLSI implementation. One set of independent speaker isolated (Mandarin digit) speech database is used as an example to demonstrate the superiority of the neural networks for spatiotemporal pattern recognition. The testing result with a reduced error rate of 7% shows that the SPNN is very attractive and effective for practical applications. The CMOS current-mode IC technology is used to implement the SPNN to achieve the objective of minimum classification error ina more direct manner. In this design, neural computation is performed in analog circuits while template information is stored in digital circuits. The prototyping speech recognition processor for the 12th LPC calculation is designed by 1.2 mu m CMOS technology. The HSPICE simulation results are also presented, which verifies the function of the designed neural system.