Browsing by Author "JOU, JY"

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TIMING-DRIVEN PARTIAL SCAN
(1995-12-01)
JOU, JY
;
CHENG, KT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This partial scan approach reduces area overhead and performance degradation caused by test logic. Given an initial design that meets a target speed, the authors' algorithm selects a set of scan flip-flops that allows the circuit to meet performance requirements after the scan logic is added. if no such set exists, the algorithm selects a set that minimizes the total area increase caused by the scan logic and the subsequent performance optimization the circuit requires to meet target speed.