Browsing by Author "JOU, SJ"
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Item type:Item, DESIGN OF A SYSTOLIC ARRAY SYSTEM FOR LINEAR STATE-EQUATIONS(1988-10-01) ;JOU, SJ ;JEN, CW ;交大名義發表 ;電控工程研究所National Chiao Tung UniversityItem type:Item, DESIGN OF ONE-DIMENSIONAL SYSTOLIC-ARRAY SYSTEMS FOR LINEAR STATE-EQUATIONS(1990-06-01) ;JEN, CW ;JOU, SJ ;交大名義發表 ;電控工程研究所National Chiao Tung UniversityItem type:Item, EMOTA - AN EVENT-DRIVEN MOS TIMING SIMULATOR FOR VLSI CIRCUITS(1990-08-01) ;SHEN, WZ ;JOU, SJ ;TAO, YS ;交大名義發表電子工程學系及電子研究所Item type:Item, EVENT-DRIVEN INCREMENTAL TIMING FAULT SIMULATOR(1993-02-01) ;JOU, SJ ;CHIOU, SH ;TAO, YS ;SHEN, WZ電控工程研究所An efficient simulator of multiple sets of multiple faults, with electrical timing information for an MOS IC. is presented. The physical faults in a real circuit are modelled more realistically by the node-short, line-open and threshold voltage degradation faults at the transistor level. On using event-driven, selective trace and mixed incremental-in-space. signal and time simulation techniques. the simulation results show that it is superior to other approaches in speed, extra memory used, and precision. Moreover, this simulator is suitable for parallel simulation in a multiprocessor system.Item type:Item, MOTA - A MOSFET TIMING SIMULATOR(1986-10-01) ;JOU, SJ ;JEN, CW ;SHEN, WZ ;LEE, CL交大名義發表Item type:Item, SIMULATABLE TIMING MODEL FOR MOS LOGIC-CIRCUIT(1987-12-01) ;JOU, SJ ;SHEN, WZ ;JEN, CW ;LEE, CL交大名義發表