Browsing by Author "JOU Shyh-Jye"

Now showing 1 - 2 of 2

ASYMMETRIC VIRTUAL-GROUND SINGLE-ENDED SRAM AND SYSTEM THEREOF
(2012-03-08)
JOU Shyh-Jye
;
Lin Jhih-Yu
;
Chuang Ching-Te
;
Tu Ming-Hsien
;
Tsai Ming-Chien
The present invention discloses an asymmetric virtual-ground single-ended SRAM and a system thereof, wherein a first inverter is coupled to a high potential and a virtual ground, and wherein the first inverter and a second inverter form a latch loop, and wherein a third inverter is electrically connected with the second inverter, and wherein the third inverter and the second inverter are jointly coupled to the high potential and a ground. A write word line and a read word line control an access transistor and a pass transistor to undertake writing and reading of signals. A plurality of asymmetric virtual-ground single-ended SRAMs forms a memory system.
STATIC RANDOM ACCESS MEMORY WITH RIPPLE BIT LINES/SEARCH LINES FOR IMROVING CURRENT LEAKAGE/VARIATION TOLERANCE AND DENSITY/PERFORMANCE
(2014-03-20)
CHUANG Ching-Te
;
YANG Hao-I
;
LU Chien-Yu
;
CHEN Chien-Hen
;
CHANG Chi-Shin
A static random access memory includes a pre-charger, a first cell column array/peripheral circuit, and a first ripple buffer. The pre-charger is connected to a first local bit line in order to pre-charge the first local bit line. The first cell column array/peripheral circuit is connected to the first local bit line and has a plurality of cells for temporarily storing data. The cells are connected to the first local bit line. The first ripple buffer is connected to the first local bit line and a second local bit line in order to send the data from the first local bit line to the second local bit line.