Browsing by Author "Jang, SL"

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Fabrication of trench-gate power MOSFETs by using a dual doped body region
(2004-07-01)
Juang, MH
;
Chen, WT
;
Ou-Yang, CI
;
Jang, SL
;
Lin, MJ
Fabrication of trench-gate power MOSFETs by using a dual doped body region has been proposed to further improve the device performance. For the usual scheme that employs a uniform doped body region, a device with a blocking voltage larger than 30 V and a specific on-state resistance of about 1.0 Omegacm can be obtained via the proper choice of trench depth, epitaxial thickness, and body doping concentration. On the other hand, a dual doped body region is produced by dual high-energy and low-energy implantation of boron dopant. By this scheme, a device with a blocking voltage larger than 30 V and a specific on-state resistance of about 0. 8 Omegacm can be further achieved. Hence, with reducing the cell pitch size to be below 2 mum, this device fabrication scheme should be promising and practical for achieving a specific on-resistance smaller than 0. 1 mOmegacm2 and a blocking voltage higher than 30 V. (C) 2004 Elsevier Ltd. All rights reserved.
Low-frequency noise characteristics of hot carrier-stressed buried-channel pMOSFETs
(1998-03-01)
Jang, SL
;
Chen, HK
;
Chang, KM
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Prestress and poststress low-frequency noise characteristics of buried-channel LDD pMOS-FETs have been studied. The devices were stressed at low gate and high drain bias, and the poststress drain current increases due to the hot-electron induced channel shortening effect. The noise measurements were carried out between 10 Hz and 100 kHz, 1/f(1.2) and generation-recombination current noises have been found in the drain current noises. The poststress 1/f(1.2) drain current noise increases in both the linear and saturation regime. This behavior is attributed to the increase of interface states and oxide electron charges after stress. (C) 1998 Elsevier Science Ltd. All rights reserved.