Browsing by Author "Javey, Ali"

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Monolithic 3D CMOS Using Layered Semiconductors
(2016-04-06)
Sachid, Angada B.
;
Tosun, Mahmut
;
Desai, Sujay B.
;
Hsu, Ching-Yi
;
Lien, Der-Hsien
Monolithic 3D integrated circuits using transition metal dichalcogenide materials and low-temperature processing are reported. A variety of digital and analog circuits are implemented on two sequentially integrated layers of devices. Inverter circuit operation at an ultralow supply voltage of 150 mV is achieved, paving the way to high-density, ultralow-voltage, and ultralow-power applications.
Quantum Well InAs/AlSb/GaSb Vertical Tunnel FET With HSQ Mechanical Support
(2015-05-01)
Zeng, Yuping
;
Kuo, Chien-I
;
Hsu, Chingyi
;
Najmzadeh, Mohammad
;
Sachid, Angada
A type-III (broken gap) band alignment heterojunction vertical in-line InAs/AlSb/GaSb tunnel FET, including a 2-nm-thin AlSb tunneling barrier is demonstrated. The impact of overlap and underlap gate is studied experimentally and supported further by quasi-stationary 2-D TCAD Sentaurus device simulations. Hydrogen silsesquioxane is used as a novel mechanical support structure to suspend the 10-nm-thin InAs drain with enough undercut to be able to demonstrate an overlap gate architecture. The overlap gate InAs/AlSb/GaSb TFET shows an ON current density of 22 mu A/mu m(2) at V-GS = V-DS = 0.4 V and the subthreshold slope is 194 mV/decade at room temperature and 46 mV/decade at 100 K.