Browsing by Author "Jean, YS"

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A new extraction algorithm for the metallurgical channel length of conventional and LDD MOSFET's
(1996-06-01)
Jean, YS
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new extraction algorithm for the metallurgical channel length of conventional and LDD MOSFET's is presented, which is based on the well-known resistance method with performing a special technique to eliminate the uncertainty of the channel length as well as to reduce the influence of the parasitic source/drain resistance on threshold-voltage determination. In particular, the metallurgical channel length is determined from a wide range of gate-voltage-dependent effective channel length at an adequate gate overdrive, The 2-D numerical analysis clearly show that the adequate gate overdrive is strongly dependent on the dopant concentration in the source/drain region, Therefore, an analytic equation is derived to determine the adequate gale overdrive for various source/drain and channel doping, It shows that higher and lower gate overdrives are needed to accurately determine the metallurgical channel length of conventional and LDD MOSFET devices, respectively. It is the first time that we can give a Correct gate overdrive to extract L(met) not only for conventional devices but also for LDD MOS devices. Besides, the parasitic source/drain resistance call also he extracted using our new extraction algorithm.
The threshold-voltage model of MOSFET devices with localized interface charge
(1997-03-01)
Jean, YS
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new analytic threshold-voltage model for a MOSFET device with localized interface charges is presented, Dividing the damaged MOSFET device into three zones, the surface potential is obtained by solving the two-dimensional (2-D) Poisson's equation, Calculating the minimum surface potential, the analytic threshold-voltage model is derived, It is verified that the model accurately predicts the threshold voltage for not only the fresh devices but also the damaged devices, Moreover, the Drain-Induced Barrier Lowering (DIBL) and substrate bias effects are also included in this model, It is shown that the screening effects due to built-in potential and drain bias dominate the impact of the localized interface charge on the threshold voltage, Calculation results show that the extension, position and density of localized interface charge are the main issues to influence the threshold voltage of a damaged MOSFET device, Simulation results using a 2-D device simulator are used to verify the validity of this model, and quite good agreements are obtained for various cases.