Browsing by Author "Jen, Chein-Wei"

Now showing 1 - 3 of 3

A 52mW 1200MIPS compact DSP for multi-core media SoC
(2006)
Ou, Shih-Hao
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Lin, Tay-Jyi
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Huang, Chao-Wei
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Kuo, Yu-Ting
;
Chao, Chie-Min
This paper presents a DSP core for multi-core media SoC, which is optimized to execute a set of signal processing tasks very efficiently. The fully-programmable core has a data-centric instruction set and a corresponding latency-insensitive microarchitecture, where the hardware design is optimized concurrently with its automatic software generator. The proposed DSP core has 3X performance (in cycles) of those found in commercial dual-core application processors with similar computing resources. The silicon implementation in UMC 0.18 mu m 1P6M CMOS technology operates at 314MHz and consumes only 52mW average power.
Method for inter-cluster communication that employs register permutation
(2005-09-15)
Jen, Chein-Wei
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Lin, Tay-Jyi
;
Lee, Chen-Chia
;
Chang, Chin-Chi
;
Liu, Chih-Wei
The present invention is a method for inter-cluster communication that employs register permutation by dynamically mapping the registers to the functional units. Because only the mapping between registers and functional units is changed and no actual data movement occurs, the present invention greatly diminishes the power consumption. Owing to the inter-cluster communication mechanism, a centralized register file can be replaced with small register sub-blocks, where the silicon area is greatly reduced, and the access time and the power consumption are also diminished.
Programmable FIR filter with adder-based computing engine
(2006)
Kuo, Yu-Ting
;
Lin, Tay-Jyi
;
Cho, Yi
;
Liu, Chih-Wei
;
Jen, Chein-Wei
This paper presents a programmable FIR core with a compact adder-based computing engine and an automatic code generator. The FIR core saves 50% area of 'conventional MAC-based cores in the 0.13 mu m implementation. Besides, the complexity-aware code generator synthesizes optimized FIR programs for a user-defined sampling period. It explores an optimal scaling factor with common subexpression elimination automatically. In our simulations, the proposed approach reduces about 10%similar to 18% computing time of MAC-based FIR cores with comparable filtering performance.