Browsing by Author "Jian, Fu-Yen"

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Abnormal Subthreshold Leakage Current at High Temperature in InGaZnO Thin-Film Transistors
(2012-04-01)
Chang, Geng-Wei
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Chang, Ting-Chang
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Jhu, Jhe-Ciou
;
Tsai, Tsung-Ming
;
Syu, Yong-En
Abnormal subthreshold leakage current is observed at high temperature in amorphous InGaZnO thin-film transistors. The transfer curve exhibits an apparent subthreshold current stretch-out phenomenon that becomes more serious with increasing temperatures. The negative bias temperature instability experiment has been used to prove high-temperature-induced hole generation. Furthermore, the transfer characteristics with different drain voltages have been also used to confirm the status of hole accumulation. These pieces of evidence clearly defined the stretch-out phenomenon, which is caused by thermal-induced hole generation and accumulation at the source region that leads to source-side barrier lowering.
Analysis of Anomalous Capacitance Induced by TAGIDL in p-Channel LTPS TFTs
(2010)
Lin, Chia-Sheng
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Chen, Ying-Chung
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Chang, Ting-Chang
;
Li, Hung-Wei
;
Chen, Shih-Ching
In this work, a mechanism of anomalous capacitance in p-channel low temperature polycrystalline silicon thin film transistors (LTPS TFTs) was investigated. In general, the effective capacitance of the LTPS TFTs was only dependent with the overlap area between the gate and source/drain under the off-state. However, the experimental results reveal that the off-state capacitance was increased with decreasing measurement frequency and/or with increasing measurement temperature. By fitting the curve of the drain current vs electric field under off-state region, it was verified that the trap-assisted gate-induced drain leakage (TAGIDL) consists of the Pool-Frenkel emission and thermal field emission. In addition, the charge density calculated from the C(gsd)-V(g) measurement also has the same dependence with electric field. This result demonstrates that the anomalous capacitance is mainly due to the TAGIDL. To suppress the anomalous capacitance, a band-to-band hot electron stress was utilized to reduce the vertical electric field between the gate and the drain. The electric field simulation was also performed by TCAD software. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3483759] All rights reserved.
Analysis of Degradation Mechanism in SONOS-TFT Under Hot-Carrier Operation
(2010-12-01)
Chen, Te-Chih
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Chang, Ting-Chang
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Chen, Shih-Ching
;
Hsieh, Tien-Yu
;
Jian, Fu-Yen
This letter investigates the degradation mechanism of polycrystalline silicon thin-film transistors with a silicon-oxide-nitride-oxide-silicon structure under OFF-state stress. During the electrical stress, the hot hole generated from band-to-band tunneling process will inject into gate dielectric, and the significant ON-state degradation (more than 1 order) indicates that the interface states are accompanied with hot-hole injection. In addition, the asymmetric I-V characteristics indicate that the interface states are located near the drain side. Moreover, the ISE-TCAD simulation tool was utilized to model the degradation mechanism and analyze trap states distribution. Although both the vertical and lateral electrical fields are factors for degradation and hot-hole injection, the degradation is mainly affected by the lateral electrical field over a critical point.
Anomalous Capacitance Induced by GIDL in P-Channel LTPS TFTs
(2009-11-01)
Lin, Chia-Sheng
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Chen, Ying-Chung
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Chang, Ting-Chang
;
Chen, Shih-Ching
;
Jian, Fu-Yen
In this letter, a mechanism of anomalous capacitance in p-channel low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) was investigated. In general, the effective capacitance was only the overlap region and independent with the frequency in LTPS TFTs under the OFF state. However, our experimental results reveal that the capacitance was related with the leakage current and that it was dependent with the measurement frequencies when operated at the OFF-state region. The increase of the capacitance value is verified to be due to the increase of the electron capacitance originating from a gate-induced drain-leakage (GIDL) one. Nevertheless, the GIDL-induced electron capacitance can be suppressed by employing band-to-band hot electron stress.
Anomalous on-current and subthreshold swing improvement in low-temperature polycrystalline-silicon thin-film transistors under Gate bias stress
(2011-03-21)
Lin, Chia-Sheng
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Chen, Ying-Chung
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Chang, Ting-Chang
;
Jian, Fu-Yen
;
Li, Hung-Wei
This work investigates an improvement in anomalous on-current and subthreshold swing (SS) in Low-temperature polycrystalline-silicon thin-film transistors after positive gate bias stress. The experimental results reveal that the improved electric properties are due to the hole trapping at SiO(2) above the lightly doped drain regions, which causes a strong electric field at the gate corners. The effect of the hole trapping is to reduce the effective channel length and the SS. Besides, the stress-related electric field was also simulated by TCAD software to verify the mechanism above. (C) 2011 American Institute of Physics. [doi:10.1063/1.3568895]
Charge-Trapping-Induced Parasitic Capacitance and Resistance in SONOS TFTs Under Gate Bias Stress
(2011-03-01)
Lin, Chia-Sheng
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Chen, Ying-Chung
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Chang, Ting-Chang
;
Jian, Fu-Yen
;
Li, Hung-Wei
This letter investigates the charge-trapping-induced parasitic resistance and capacitance in silicon-oxide-nitride-oxide-silicon thin-film transistors under positive and negative dc bias stresses. The results identify a parasitic capacitance in OFF-state C-V curve caused by electrons trapped in the gate insulator near the defined gate region during the positive stress, as well as the depletion induced by those trapped electrons. Meanwhile, the induced depletions in source/drain also degraded the I-V characteristic when the gate bias is larger than the threshold voltage. However, these degradations slightly recover when the trapped electrons are removed after negative bias stress. The electric field in the undefined gate region is also verified by TCAD simulation software.
Degradation of Low Temperature Polycrystalline Silicon Thin Film Transistors under Negative Bias Temperature Instability Stress with Illumination Effect
(2010)
Lin, Chia-Sheng
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Chen, Ying-Chung
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Chang, Ting-Chang
;
Li, Hung-Wei
;
Hsu, Wei-Che
This work investigates negative bias temperature instability (NBTI) in low temperature polycrystalline silicon thin film transistors (LTPS TFTs) in a darkened and in an illuminated environment of different light intensities. Experimental results reveal that the generations of interface state density (N(it)) are identical under various illuminated intensity NBTI stresses. Nevertheless, the degradation of the grain boundary trap (N(trap)) under illumination was more significant than that for the darkened environment, with degradation increasing as illumination intensity increases. This phenomenon is mainly caused by the extra number of holes generated during the illuminated NBTI stress. The increased N(trap) degradation leads to an increase in the darkened environment leakage current. This indicates that more traps are generated in the drain junction region than from carrier tunneling via the trap, resulting in leakage current. Conversely, an increase in N(trap) degradation results in a decrease in the photoleakage current. This indicates that the number of recombination centers increases in the poly-Si bulk, affecting photosensitivity in LTPS TFTs.
Developments in nanocrystal memory
(2011-12-01)
Chang, Ting-Chang
;
Jian, Fu-Yen
;
Chen, Shih-Cheng
;
Tsai, Yu-Ting
;
電子工程學系及電子研究所
Since the 1990s, portable electronic products have been a prominent part of our daily lives; and many of these devices require flash memories. The floating-gate (FG) structure, invented by Sze and Kahng at Bell Labs in 1967, forms the primary technology necessary to construct flash memories(1), Fig. 1a. In order to meet the demands of product miniaturization, the shrinking of transistors has evolved as a method to not only pack more devices into a given area, but also improve the switching speed. In such a situation, conventional nonvolatile memory (FG) suffers from certain physical limitations, such as an insufficient tunneling oxide thickness from the continual scaling down of the device structures(2). Because the floating gate (as a charge storing layer) is conductive, all charge will be lost if a leakage path appears in the tunneling oxide, resulting in a serious reliability issue for memory applications. Discrete nanocrystal memory was first proposed by IBM in 1995, and by the early 2000s researchers were already considering it to be a promising candidate for the solution of the scaling problem(3) (Fig. 1b). In addition, nanocrystal memory has a two bit per cell storage capability due to its discrete electron storing center. This means that more data can be stored in one memory cell, which readily increases the memory density(4).
Effect of Lateral Body Terminal on Silicon-Oxide-Nitride-Oxide-Silicon Thin-Film Transistors
(2011-10-01)
Li, Hung-Wei
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Chang, Ting-Chang
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Chang, Geng-Wei
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Lin, Chia-Sheng
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Tsai, Tsung-Ming
We investigate lateral-body-terminal silicon-oxide-nitride-oxide-silicon thin-film transistors (LBT SONOS TFTs) under erasing operation. These devices have superior erasing efficiency by gate as well as lateral body electrode exerting bias. The erasing mechanism of LBT SONOS TFTs has been illustrated by the energy band diagrams. Holes gain sufficient energy by the electric field in the deep-depletion region to surmount the tunneling oxide barrier because of exerting body bias under erasing operation. In addition, the lateral body terminal exerting bias can enhance the erasing efficiency and is confirmed by different erasing conditions and structures. In addition, to verify the hole current injecting from the lateral body site, the size effect of LBT SONOS TFTs is also discussed.
Illumination-Assisted Negative Bias Temperature Instability Degradation in Low Temperature Polycrystalline Silicon Thin-Film Transistors
(2009)
Lin, Chia-Sheng
;
Chen, Ying-Chung
;
Chang, Ting-Chang
;
Hsu, Wei-Che
;
Chen, Shih-Ching
In this work, the negative bias temperature instability (NBTI) in low temperature polycrystalline silicon thin-film transistors in a darkened and in an illuminated environment was investigated. Experimental results reveal that the generation of interface state density (N(it)) showed no change between the different NBTI stresses. Nevertheless, the degradation of the grain boundary trap (N(trap)) under illumination was more significant than that in the darkened environment. This phenomenon is mainly caused by the extra number of holes generated during the illuminated NBTI stress.
Improvement in the bias stability of amorphous InGaZnO TFTs using an Al2O3 passivation layer
(2013-09-01)
Huang, Sheng-Yao
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Chang, Ting-Chang
;
Chen, Min-Chen
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Chen, Te-Chih
;
Jian, Fu-Yen
This work presents the light-color-dependent negative bias stress (NBIS) effect on amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) with Al2O3 passivation layer. The colors of incident photon are varied from red to blue, that incident photon energies are all lower than the optical band gap of IGZO (3.2 eV). The experimental results show that the Al2O3 passivated devices present stable electrical behaviors under different incident lights (Delta V-T<0.1 V of dark and red, Delta V-T<1 V of green, and Delta V-T<4 V of blue), whereas the unpassivation devices exhibit observable negative shifts during NBIS (Delta V-T<1 V of dark and red, Delta V-T>8 V of green, and Delta V-T>15 V of blue). The degradation mechanism of the negative bias stress under illumination of a-IGZO TFTs is dominated by the photo-generated hole trapping at the gate insulator and/or interface between insulator and channel. In this result, the Al2O3 passivation layer can effectively passivate the defect in the a-IGZO film, reducing electron hole pair generated during the illumination processed. Crown Copyright (C) 2012 Published by Elsevier B.V. All rights reserved.
Investigating bipolar resistive switching characteristics in filament type and interface type BON-based resistive switching memory
(2013-02-01)
Tseng, Hsueh-Chih
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Chang, Ting-Chang
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Cheng, Kai-Hung
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Huang, Jheng-Jie
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Chen, Yu-Ting
This paper studies the effect of doping on BON-based resistive switching characteristics. Typical bipolar resistive switching behavior can be observed in Pt/BON/TiN and Pt/BON:Gd/TiN devices. The conductive path(s) of the Pt/BON/TiN is vacancy-dominated while the Pt/BON:Gd/TiN is metal-dominated. Additionally, there is an atypical bipolar resistive switching in the Gd-doping device. This atypical characteristic has not only a size effect, but also a lower operating current. The resistance transitions are due to the variation in conductance of the switching layer, which is clearly influenced by the different area size. A mechanism is proposed to explain this atypical characteristic. (c) 2012 Elsevier B.V. All rights reserved.
Investigating Degradation Behavior of InGaZnO Thin-Film Transistors induced by Charge-Trapping Effect under DC and AC Gate-Bias Stress
(2012)
Hsieh, Tien-Yu
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Chang, Ting-Chang
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Chen, Te-Chih
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Tsai, Ming-Yen
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Chen, Yu-Te
This paper investigates the degradation mechanism of amorphous InGaZnO thin-film transistors under DC and AC gate bias stress. Comparing the degradation behavior at equal accumulated effective stress time, more pronounced threshold voltage shift under AC positive gate bias stress in comparison with DC stress indicates extra electron-trapping phenomenon occurs in the duration of rising/falling time in pulse. Contrarily, illuminated AC negative gate bias stress exhibits much less threshold voltage shift than DC stress, which suggesting the photo-generated hole does not has sufficient time to drift to the interface of IGZO/gate insulator and causes hole-trapping under AC operation. Since the evolution of threshold voltage fits the stretched-exponential equation well, the different degradation tendencies under DC/AC stress can be attributed to the different electron-and hole-trapping efficiencies, and this is further verified by varying pulse waveform.
Investigating the degradation behavior caused by charge trapping effect under DC and AC gate-bias stress for InGaZnO thin film transistor
(2011-07-11)
Chen, Te-Chih
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Chang, Ting-Chang
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Hsieh, Tien-Yu
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Lu, Wei-Siang
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Jian, Fu-Yen
This letter investigates the degradation mechanism of amorphous indium-gallium-zinc oxide thin-film transistors under gate-bias stress. The larger V(t) shift under positive AC gate-bias stress when compared to DC operation indicates that an extra electron trapping mechanism occurs during rising/falling time during the AC pulse period. In contrast, the degradation behavior under illuminated negative gate-bias stress exhibits the opposite degradation tendency. Since electron and hole trapping are the dominant degradation mechanisms under positive and illuminated negative gate-bias stress, respectively, the different degradation tendencies under AC/DC operation can be attributed to the different trapping efficiency of electrons and holes. (C) 2011 American Institute of Physics. [doi: 10.1063/1.3609873]
Investigating the improvement of resistive switching trends after post-forming negative bias stress treatment
(2011-09-26)
Tseng, Hsueh-Chih
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Chang, Ting-Chang
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Huang, Jheng-Jie
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Yang, Po-Chun
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Chen, Yu-Ting
This paper investigates the improvement of resistive switching trends after post-forming negative bias stress treatment of a Pt/Yb(2)O(3)/TiN device that has undergone positive bias forming process for activation. After the treatment, characteristics of the conductive filament, such as the temperature dependence of resistivity and transition mechanism, undergo changes. Furthermore, this treatment causes the conductive filament to transform from being primarily composed of vacancies to being metallic Yb dominant, which not only reduces operation voltages such as V(set) and V(reset) but also improves the on/off ratio. In reliability tests, the device has stable retention. (C) 2011 American Institute of Physics. [doi: 10.1063/1.3645004]
Investigation of gate-bias stress and hot-carrier stress-induced instability of InGaZnO thin-film transistors under different environments
(2013-09-01)
Hsieh, Tien-Yu
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Chang, Ting-Chang
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Chen, Te-Chih
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Tsai, Ming-Yen
;
Chen, Yu-Te
This paper investigates the temperature and ambiance effects on various reliability issues for InGaZnO thin film transistors with an organic passivation layer. Hot-carrier stress and gate-bias stress are carried out under different environmental temperatures and ambient gases. The device exhibits relatively good stability under room temperture, whereas high temperature enhances degradation. Futhermore, different degradation behaviors after gate-bias stress in atmosphere and in vacuum can be attributed to gas adsorption/desorption-induced instability. Moreover, capacitance-voltage measurement techinique is utilized to analyze the degradation mechanism and to extract the density of state (DOS). The result reveals that the threshold voltage shift after both hot-carrier and gate-bias stress originates from the charge-trapping effect at the interface of gate insulator and active layer, with the extra trap states generated during stress responsible for C-V curve distortion. In addition, the asymmetric degradation behavior of gate-to-drain capacitance (Cgd) and gate-to-source capacitance (Cgs) indicates that trap states are generated near the drain side. (C) 2012 Elsevier B.V. All rights reserved.
N2O Plasma Treatment Suppressed Temperature-dependent Point Defects Formation with Amorphous Indium-Gallium-Zinc-Oxide Thin Film Transistors
(2012)
Jhu, Jhe-Ciou
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Chang, Ting-Chang
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Chang, Geng-Wei
;
Syu, Yong-En
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Tsai, Tsung-Ming
Abnormal sub-threshold leakage current is observed at high temperature in amorphous Indium-Gallium-Zinc-Oxide Thin Film Transistors (a-IGZO TFTs). To confirm this phenomenon\'s dependence on the defects of a-IGZO active layer, this paper examines a device fabricated with N2O plasma treatment at a-IGZO film. This phenomenon only appears in the as-fabricated device, but not in the device with N2O plasma treatment, which is experimentally verified. N2O plasma treatment of a-IGZO TFTs enhance the thin film bonding strength, which could suppress the formation of temperature-dependent point defects. The point defects could be generated from oxygen atoms leaving their original sites above 400K. The N2O plasma treatment devices have better stability performance than as-fabricated devices. The results suggested that the density of point states for a-IGZO TFTs with N2O plasma treatment is much lower than that as-fabricated. The N2O plasma repairs the point defect to suppress temperature-dependent sub-threshold leakage current.
N2O plasma treatment suppressed temperature-dependent sub-threshold leakage current of amorphous indium-gallium-zinc-oxide thin film transistors
(2013-09-01)
Chang, Geng-Wei
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Chang, Ting-Chang
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Jhu, Jhe-Ciou
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Tsai, Tsung-Ming
;
Syu, Yong-En
N2O plasma treatment suppressed the temperature-dependent sub-threshold leakage current of amorphous indium-gallium-zinc-oxide thin film transistors (a-IGZO TFTs). For untreated devices, the transfer curve exhibited abnormal electrical properties at high temperature. The abnormal electrical properties are explained by the energy band diagrams for both forward and reverse sweep. Above 400 K, holes can be generated from trap-assisted transition, and drift to the source side which induces source barrier lowering. The source side barrier lowering enhances electron injection from the source to channel and causes an apparent sub-threshold leakage current. This phenomenon, which is experimentally verified, only appears in the device without N2O plasma treatment, but not in the device with N2O plasma treatment. The results suggested that the density of states for a-IGZO with N2O plasma treatment is much lower than that without plasma treatment. (C) 2012 Elsevier B.V. All rights reserved.
NBTI Degradation in LTPS TFTs Under Mechanical Tensile Strain
(2011-07-01)
Lin, Chia-Sheng
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Chen, Ying-Chung
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Chang, Ting-Chang
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Jian, Fu-Yen
;
Hsu, Wei-Che
This letter investigates the negative-bias temperature instability (NBTI) degradation of p-channel low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs) under mechanical tensile stress. Experimental results reveal that the interface state density N(it) and grain boundary trap density N(trap) of tensile-strained LTPS TFTs are more pronounced than those of unstrained LTPS TFTs. Extracted density of states and conduction activation energy E(a) both show increases due to the strained Si-Si bonds, which implies that strained Si-Si bonds are able to react with dissociated H during NBTI stress. Therefore, NBTI degradation is more significant after tensile strain than in an unstrained condition.
On the Origin of Gate-Induced Floating-Body Effect in PD SOI p-MOSFETs
(2011-07-01)
Dai, Chih-Hao
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Chang, Ting-Chang
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Chu, An-Kuo
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Kuo, Yuan-Jui
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Jian, Fu-Yen
This letter systematically investigates the origin of gate-induced floating-body effect (GIFBE) in partially depleted silicon-on-insulator p-type MOSFETs. The experimental results indicate that GIFBE causes a reduction in the electrical oxide field, leading to an underestimate of negative-bias temperature instability degradation. This can be partially attributed to the electrons tunneling from the process-induced partial n(+) polygate. However, based on different operation conditions, we found that the dominant origin of electrons was strongly dependent on holes in the inversion layer under source/drain grounding. This suggests that the mechanism of GIFBE at higher voltages is dominated by the proposed anode electron injection model, rather than the electron valence band tunneling widely accepted as the mechanism for n-MOSFETs.