Browsing by Author "Jiang, Iris Hui-Ru"

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3DICE: 3D IC Cost Evaluation Based on Fast Tier Number Estimation
(2011)
Chan, Cheng-Chi
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Yu, Yen-Ting
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Jiang, Iris Hui-Ru
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
During the billion transistor era, 3D stacking offers an attractive solution for the difficulties resulting from large-scale design complexities. Moreover, 3D stacking can benefit performance, power, bandwidth, footprint, and heterogeneous technology mixing. However, before adopting the 3D design strategy, this study seeks to understand how much cost is required to trade these benefits. This paper proposes a 3D IC cost evaluation framework based on fast tier number estimation Using a reformulated Rent's rule, this study efficiently determines the number k of tiers to minimize the through-silicon via count and then automatically partitions a gate-level netlist into k tiers to minimize the total cost. This study conducted experiments on eight industrial test cases to show cost efficiency and effectiveness. Moreover, results prove that the reformulated Rent's rule indicates a strong correlation between the tier number and through-silicon via usage.
Accurate Process-Hotspot Detection Using Critical Design Rule Extraction
(2012)
Yu, Yen-Ting
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Chan, Ya-Chung
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Sinha, Subarna
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Jiang, Iris Hui-Ru
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Chiang, Charles
In advanced fabrication technology, the sub-wavelength lithography gap causes unwanted layout distortions. Even if a layout passes design rule checking (DRC), it still might contain process hotspots, which are sensitive to the lithographic process. Hence, process-hotspot detection has become a crucial issue. In this paper, we propose an accurate process-hotspot detection framework. Unlike existing DRC-based works, we extract only critical design rules to express the topological features of hotspot patterns. We adopt a two-stage filtering process to locate all hotspots accurately and efficiently. Compared with state-of-the-art DRC-based works, our results show that our approach can reach 100% success rate with significant speedups.
Analog Placement and Global Routing Considering Wiring Symmetry
(2010)
Yang, Yu-Ming
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Jiang, Iris Hui-Ru
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電機學院
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電子工程學系及電子研究所
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College of Electrical and Computer Engineering
Unlike the mature and highly automatic flow for digital layout generation, the existing method to generate an analog layout is far from automatic because it highly depends on the designer\'s expertise. Prior endeavors are mainly dedicated to analog placement because they consider only the device symmetry constraint. This paper raises the wiring symmetry issue to analog layout: wiring symmetry is as crucial as device symmetry. Hence, we propose an analog placement and global routing algorithm to consider both types of symmetry constraints. During placement, we utilize the device folding technique to enhance the flexibility and feasibility on symmetry. Our results show that our algorithm can produce a promising initial layout to speed up the analog design process.
Analytical Clustering Score with Application to Postplacement Register Clustering
(2016-07)
Xu, Chang
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Luo, Guojie
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Li, Peixin
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Shi, Yiyu
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Jiang, Iris Hui-Ru
Circuit clustering is usually done through discrete optimizations to enable circuit size reduction or design-specific cluster formation. In this article, we are interested in the register-clustering technique for clock-power reduction by leveraging new opportunities introduced by multibit flip-flop (MBFF). Currently, INTEGRA is the only existing postplacement MBFF clustering optimizer with a subquadratic time complexity. However, it severely degrades the wirelength, especially for realistic designs, which may nullify the benefits of MBFF clustering. In contrast, we formulate an analytical clustering score with a nonlinear programming framework, in which the wirelength objective can be seamlessly integrated and the solver has empirical subquadratic time complexity. With the MBFF library, the application of our analytical clustering method achieves comparable clock power to the state-of-the-art techniques, but further reduces the wirelength by about 25%. Even without the MBFF library, we can still achieve 30% clock wirelength reduction. In addition, the proposed method can potentially be integrated into an in-placement MBFF clustering solver and be applied to other problems that require formulating clustering scores in their objective functions.
Configurable Rectilinear Steiner Tree Construction for SoC and Nano Technologies
(2008)
Jiang, Iris Hui-Ru
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Yu, Yen-Ting
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The rectilinear Steiner minimal tree (RSMT) problem is essential in physical design. Moreover, the variant constraints for fabrication issues, including obstacle avoidance, multiple routing layers, layer-specific routing directions, cannot be ignored during RSMT construction for modern SoC and nano technologies. This paper proposes a construction-by-correction approach for obstacle-avoiding preferred direction rectilinear Steiner tree construction. Experimental results show that our algorithm is promising and outperforms the state-of-the-art works.
Criticality-Dependency-Aware Timing Characterization and Analysis
(2015)
Yang, Yu-Ming
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Tam, King Ho
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Jiang, Iris Hui-Ru
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
For nanometer design, conventional timing analysis may generate over-optimistic results on criticality-dependent paths. A late arrival time at the data input of a flip-flop lengthens the propagation delay from the clock pin to the data output of this flip-flop, thus degrading the timing margins of paths launching from this flip-flop. To remove the optimism, in this paper, we first propose a simple yet effective triangle model to characterize the criticality-dependency effect. Then, we devise a novel criticality-dependency-aware timing analysis flow, which is seamlessly integrated with the common static timing analysis flow. Experimental results show that our approach can effectively analyze the criticality-dependency effect: Based on the proposed triangle model, we can accurately identify all timing-risky Hip Hops and capture the induced timing margin degradation.
DATC RDF-2019: Towards a Complete Academic Reference Design Flow
(2019-01-01)
Chen, Jianli
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Jiang, Iris Hui-Ru
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Jung, Jinwook
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Kahng, Andrew B.
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Kravets, Victor N.
We describe a new RDF-2019 release of the IEEE CEDA DATC Robust Design Flow (RDF). RDF-2019 enhances the DATC RDF to span the entire RTL-to-GDS IC implementation flow, from logic synthesis to detailed routing. The new release represents a significant revision of the previously-reported RDF-2018 flow. Noteworthy vertical extensions include addition of logic synthesis starting from pure behavioral RTL Verilog RTL; floorplanning that includes initial DEF creation, I/O placement and PDN layout generation; and clock tree synthesis between placement legalization and global routing. A number of horizontal extensions to RDF are achieved by incorporating additional tool options at the static timing analysis, global placement, gate sizing, and detailed routing stages of the flow. Further, for the first time, multiple open-source realizations of the entire RDF tool chain are available. Last, RDF-2019 provides significantly enhanced support of and interoperability with industry-standard tools and design formats (LEF/DEF, SPEF, Liberty, SDC, etc.). We illustrate the configuration and use of RDF-2019, with example results on open as well as commercial design enablements.
DATC RDF: An Academic Flow from Logic Synthesis to Detailed Routing
(2018-01-01)
Jung, Jinwook
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Jiang, Iris Hui-Ru
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Chen, Jianli
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Lin, Shih-Ting
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Li, Yih-Lang
In this paper, we present DATC Robust Design Flow (RDF) from logic synthesis to detailed routing. We further include detailed placement and detailed routing tools based on recent EDA research contests. We also demonstrate RDF in a scalable cloud infrastructure. Design methodology and cross-stage optimization research can be conducted via RDF.
DATC RDF: Robust Design Flow Database
(2017-01-01)
Jung, Jinwook
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Lee, Pei-Yu
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Wu, Yan-Shiun
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Darav, Nima Karimpour
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Jiang, Iris Hui-Ru
In this paper, we present DATC Robust Design Flow Database covering the stages from logic synthesis to physical design [1]. Based on this database, design flow and cross-stage optimization research can be conducted via various EDA tools developed from academia.
DRC-Based Hotspot Detection Considering Edge Tolerance and Incomplete Specification
(2014)
Yu, Yen-Ting
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Jiang, Iris Hui-Ru
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Zhang, Yumin
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Chiang, Charles
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交大名義發表
To improve the yield in current manufacturing processes, the problematic layout configurations, so-called process-hotspots, should be detected and replaced with yield friendly patterns. A hotspot pattern with edge tolerances and incomplete specifications, where edges may vary in a certain range and any layout configurations may exist in its ambit regions, can sufficiently and generally represent a process-hotspot. This type of hotspots, however, cannot be efficiently or correctly detected by using the state-of-the-art string-matching-based method. In this paper, we present an accurate and efficient DRC-based hotspot detection framework to handle hotspot patterns with edge tolerances and incomplete specifications. Unlike existing DRC-based work, which handles only completely specified patterns, we extract critical design rules to represent all possible topologies of hotspot patterns with edge tolerances and incomplete specifications. We further order these rules to iteratively reduce the search regions of a layout during design rule checking. Then, we apply longest common subsequence and linear scan to locate all hotspots accurately and efficiently. Compared with the state-of-the-art work, experimental results show that our approach can reach promising success rates with significant speedups.
ECOS: Stable Matching Based Metal-Only ECO Synthesis
(2012-03-01)
Jiang, Iris Hui-Ru
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Chang, Hua-Yu
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
To ease the time-to-market pressure and save the photomask cost, metal-only ECO realizes the last-minute design changes by revising the photomasks of metal layers only. This task is challenging because the pre-injected spare cells are limited in number and in cell types. Metal-only ECO has to implement these functional and/or timing changes using available spare cells. In this paper, we propose a stable matching based metal-only ECO synthesizer, named ECOS, that can implement the incremental design changes correctly without sacrificing timing and routability. The experiments are conducted on nine industrial testcases. These testcases reflect the real difficulties faced by designers and our results show that ECOS is promising for all of them.
Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog
(2014-11-01)
Cheng, An-Che
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Yen, Chia-Chih (Jack)
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Val, Celina G.
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Bayless, Sam
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Hu, Alan J.
SystemVerilog provides powerful language constructs for verification, and one of them is the covergroup functional coverage model. This model is designed as a complement to assertion verification, that is, it has the advantage of defining cross-coverage over multiple coverage points. In this article, a coverage-driven verification (CDV) approach is formulated as a simultaneous Boolean satisfiability (SAT) problem that is based on covergroups. The coverage bins defined by the functional model are converted into Conjunction Normal Form (CNF) and then solved together by our proposed simultaneous SAT algorithm PLNSAT to generate stimuli for improving coverage. The basic PLNSAT algorithm is then extended in our second proposed algorithm GPLNSAT, which exploits additional information gleaned from the structure of SystemVerilog covergroups. Compared to generating stimuli separately, the simultaneous SAT approaches can share learned knowledge across each coverage target, thus reducing the overall solving time drastically. Experimental results on a UART circuit and the largest ITC benchmark circuits show that the proposed algorithms can achieve 10.8x speedup on average and outperform state-of-the-art techniques in most of the benchmarks.
Efficient Search of Layout Hotspot Patterns for Matching SEM Images using Multilevel Pixelation
(2019-01-01)
Tseng, Sean Shang-En
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Chang, Wei-Chun
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Jiang, Iris Hui-Ru
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Zhu, Jun
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Shiely, James P.
Layout features become highly susceptible to lithography process fluctuations due to the widening subwavelength lithography gap. Problematic layout patterns incur poor printability even if they pass design rule checking. These hotspots should be detected and removed at early design phases to improve manufacturability. While existing studies mainly focus on hotspot detection and pattern classification, hotspot pattern library generation is rarely addressed in literature but crucial to the effectiveness and efficiency of hotspot detection. For an advanced process, in addition to yield-limiting patterns inherent from old processes and computation intensive lithography simulation, defect silicon images (SEM images) inspected from test wafers provide more realistic process-dependent hotspots. For facilitating hotspot pattern library generation, we raise a pattern matching problem of searching design layout patterns that may induce problematic SEM images. The key challenge is the various shape distortions between an SEM image and corresponding design layouts. Directly matching either feature points or shapes of both is thus not applicable. We observe that even with shape distortions, matched design layouts and the SEM image have similar density distribution. Therefore, in this paper, we propose an efficient multilevel pixilation framework to seek layout clips with similar density distribution from coarse- to fine-granularities to an SEM image. The proposed framework possesses high parallelism. Our results show that the proposed method can effectively and efficiently identify matched layout pattern candidates.
Fast Low Power Rule Checking for Multiple Power Domain Design
(2017-01-01)
Lu, Chien-Pang
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Jiang, Iris Hui-Ru
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Power management via multiple power domains can effectively save power by dynamically turning off idle domains. To control domains of a design, introducing low power intent complicates the physical implementation and verification process. During the physical implementation stage, the optimization or manual ECO could be tedious, and error-prone on power/ground signal connections. Therefore, in this paper, we focus on low power rule checking at the physical implementation stage for multiple power domain design. Existing methods adopt an iterative approach, which identifies one error at a time, thus possibly requiring multiple iterations. Different from them, we propose a fast low power rule checking approach to detect all errors at one time. To do so, we separate all paths into inner domain and cross-domain paths and extract cross-domain net topology before power rule verification. Based on the global topology, we can verify the correctness of connections and detect all errors at the same time. Experimental results show the effectiveness and efficiency of our approach, achieving 3.62X speedups to detect all errors compared with the iterative approach. Moreover, our approach can identify complicated bugs to facilitate subsequent bug fixing.
FastPass: Fast Timing Path Search for Generalized Timing Exception Handling
(2018-01-01)
Lee, Pei-Yu
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Jiang, Iris Hui-Ru
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Chen, Tung-Chieh
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
As design complexity rapidly grows, a modem design contains more complex constraints and has more clock domains. To these stringent timing requirements, a design is iteratively optimized. Along with intensive optimizations, fast timing analysis guiding designers to fix timing violations is desired. Thus far, previous works have focused on either timing exception handling or path search only. Different from them, in this paper, we tackle these two issues together for the urgent need in modem design. We first generalize timing exceptions to model all common timing exceptions and other path-specific timing quantities. Then, we propose a novel timing analysis flow that performs fast path search for generalized timing exception handling. Furthermore, we develop three delicate techniques to achieve fast path search, including local slack bounds, dynamic slack recovering, and slack priority queue. Experimental results show that our model is general, and our flow is promising with high efficiency and scalability.
Functional ECO Using Metal-Configurable Gate-Array Spare Cells
(2014)
Chang, Hua-Yu
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Jiang, Iris Hui-Ru
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Chang, Yao-Wen
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Metal-configarable gate-array spare cells, which have versatile functionality, are developed to overcome the inflexibility of standard spare cells used in conventional metal-only engineering change order (ECO). In this paper, we focus on functional ECO optimization using the new type of spare cells to fully exploit its strength. We observe that this functional LCD problem has the nature of dynamic logical and physical costs for at spare gate arrays. Unlike existing functional E0 works, which perform technology snapping based on ECO patches, we perform reverse mapping from spare gate arrays to handle these dynamic costs. We devise a spare array relation graph to record geometrical adjacency among spare gate arrays and interleave with the and-inverter network of ECO patches. To avoid redundant traversal and monitor the dynamic costs, we adopt A* search to simultaneously traverse and imp between the logical LCD network and the physical spare array relation graph.
GasStation: Power and Area Efficient Buffering for Multiple Power Domain Design
(2015-01-01)
Lu, Chien-Pang
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Jiang, Iris Hui-Ru
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Hsu, Chin-Hsiung
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Power management, which can be effectively realized by dynamically turning on/off power domains, is a key concern for modern mobile devices. Leakage power in multiple power domain design is usually dominated by nets passing through different power domains because prior work allocates always-on buffers for these feedthrough nets. Unlike prior work, which uses always-on buffers, we create specific power islands with normal buffers in this paper; these power islands gather buffers on feedthrough nets together to share the power and area overhead. The buffer allocation is performed by a wave-propagation based algorithm, named GasStation. Compared with the conventional always-on buffer approach, experimental results show that GasStation can reduce 75% buffer area, 34% buffer count, 80% leakage power, and 8% wirelength on feedthrough nets in eight industrial smart phone designs.
Generic Integer Linear Programming Formulation for 3D IC Partitioning
(2012-11-01)
Lee, Wan-Yu
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Jiang, Iris Hui-Ru
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Mei, Tsung-Wan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The success of 3D IC requires novel EDA techniques. Although many EDA techniques exist, this paper focuses on 3D IC partitioning, especially at the architectural level to maximize its benefits. First, logical formulations for 3D IC partitioning problems are derived and then the formulations are transformed into integer linear programs (ILPs). The ILP formulation can minimize the usage of vertical interconnects subject to the footprint and power consumption constraints. The flexibility of ILP formulation can be demonstrated by extending the generic ILP formulation to support designs with multiple supply voltages. This study proposes ILP reduction techniques to speed up the convergence. Experimental results based on the GSRC benchmark show that our approach converges efficiently. Moreover, our approach is flexible and can readily extend to the partitioning problems with variant objectives and constraints, and with different abstraction levels, for example, from the architectural level down to the physical level. This flexibility makes the ILP formulation a superior alternative to 3D IC partitioning problems.
GENERIC INTEGER LINEAR PROGRAMMING FORMULATION FOR 3D IC PARTITIONING
(2009)
Jiang, Iris Hui-Ru
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The success of 3D ICs requires novel EDA techniques. Among them, this paper focuses on 3D IC partitioning, especially at the architectural level to maximize its benefits. We first derive logical formulations for 3D IC partitioning problems and then transform the formulations into integer linear programs (ILPs). The ILPs can minimize the footprint and the usage of vertical interconnects simultaneously. Our results conducted on the GSRC benchmark show that our approach outperforms the extended multi-way partitioning method in the usage of vertical interconnects under the same footprint settings. More importantly, our approach is very flexible and can readily extend to the partitioning problems with variant objectives and constraints, and with different abstract levels, e.g., from the architectural level down to the physical level. This flexibility makes the ILP formulations superior alternatives to the 3D IC partitioning problems.
Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing Balancing
(2019-01-01)
Chang, Ya-Chu
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Lin, Tung-Wei
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Jiang, Iris Hui-Ru
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Nam, Gi-Joon
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電子工程學系及電子研究所
As the wide adoption of FinFET technology in mass production, dynamic power becomes the bottleneck to achieving low power. Therefore, clock power reduction is crucial in modern IC design. Register clustering can effectively save clock power because of significantly reducing the number of clock sinks and register pin capacitance, clock routed wirelength, and the number of clock buffers. In this paper, we propose effective mean shift to naturally form clusters according to register distribution without placement disruption. Effective mean shift fulfills the requirements to be a good register clustering algorithm because it needs no prespecified number of clusters, is insensitive to initializations, is robust to outliers, is tolerant of various register distributions, is efficient and scalable, and balances clock power reduction against timing degradation. Experimental results show that our approach outperforms state-of-the-art work on power and timing balancing, as well as efficiency and scalability.