Browsing by Author "Jiang, Jheng-Yi"

Now showing 1 - 2 of 2

Numerical Study of 4H-SiC UMOSFETs with Split-Gate and P plus Shielding
(2020-03-01)
Jiang, Jheng-Yi
;
Wu, Tian-Li
;
Zhao, Feng
;
Huang, Chih-Fang
;
國際半導體學院
In this paper, performances of a 4H-SiC UMOSFET with split gate and P+ shielding in different configurations are simulated and compared, with an emphasis on the switching characteristics and short circuit capability. A novel structure with the split gate in touch with the P+ shielding is proposed. The key design issues for 4H-SiC UMOSFETs are trench gate dielectric protection and reverse transfer capacitance Crss reduction. Based on simulation results, it is concluded that a UMOSFET with a gate structure combining split gate grounded to the trench bottom protection P+ shielding layer and a current spreading layer is achieved to yield the best compromise between conduction, switching, and short circuit performance. The split-gate design can effectively reduce Crss by shielding the coupling between the gate electrode and the drain region. The P+ shielding design not only protects the oxide at trench bottom corners but also minimizes the short channel effect due to drain-induced barrier lowing and the channel length modulation. Trade-off of the doping concentration of current spreading layer for UMOSFET is also discussed. A heavily doped current spreading layer may increase Crss and influence the switching time, even though R-ON,R-SP is reduced.
Study on the effects of Si implantation on the interface of 4H-SiC lateral MOSFETs
(2020-04-01)
Jiang, Jheng-Yi
;
Hung, Jia-Qing
;
Huang, Pin-Wei
;
Wu, Tian-Li
;
Huang, Chi-Fang
In this study, Si implantation was used to improve the interface properties of SiC/SiO2 in 4H-SiC lateral MOSFETs. In lateral n-channel MOSFETs, a 4%-6% improvement on the linear and saturation current was observed with Si implantation, From high/low-frequency CV measurements, the Si implanted n-type MOS capacitor showed a 20% lower interface state density than the non-implanted ones at an energy level of E-C - E = 0.2 eV, without degrading oxide integrity. Lateral p-channel MOSFETs, on the other hand, showed a 36.5% reduction in the linear current and a 16.6% reduction in the saturation current with Si implantation. Furthermore, the temperature coefficients of lateral and vertical MOSFETs implanted, by Si ere monitored up to 175 degrees C. The temperature coefficients of the Si-implanted n-channel and p-channel lateral MOSFETs were nearly identical to those of their non-implanted counterparts. (C) 2020 The Japan Society of Applied Physics