Browsing by Author "Jiang, TY"

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An efficient logic extraction algorithm using partitioning and circuit encoding
(2004)
Huang, L
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Jiang, TY
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Jou, JY
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Huang, HL
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電子工程學系及電子研究所
Nowadays, finding subcircuits in a larger circuit is primarily solved by using various heuristics based on graph isomorphism. These approaches are addressed on identify g one specific subcircuit at each time and may take numerous runs if many subcircuits need to be extracted. Therefore, they are not quite suitable for converting the whole circuit represented at transistor-level to a gate-level netlist. We present a logic extraction approach based on dc-connected component (DCC) partition and modified circuit-encoding algorithm to extract all kinds of subscircuits from the input circuit concurrently such that we can. map each subcircuit represented as transistor level netlist to its corresponding logic gate. This mapping relation can be exploited to speed up the simulation of large circuits. Experiments on several real circuits, including sequential logic ones and combination logic ones, show the near-linear performance in run time and memory usage.
Effective error diagnosis for RTL designs in HDLS
(2002)
Jiang, TY
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Liu, CNJ
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Jou, JY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
We propose an effective approach to diagnose multiple design errors in HDL designs with only one erroneous test case. Error candidates will be greatly reduced while ensuring that true erroneous statements are included in, The probability of correctness for each potential erroneous statement will be estimated such that the most suspected statements are reported first. Experiments show that the size of error candidates is indeed small and the estimation for the probability of correctness for potential error candidates is accurate.
Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs
(2005)
Jiang, TY
;
Liu, CNJ
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Debugging priority is a helpful technique to assist debugging faulty HDL designs [9]. However, debugging priority obtained by sorting confidence score is not good enough due to the inaccuracy in estimating likelihood of correctness for error candidates. Therefore, we developed Refined Confidence Score for deriving better debugging priority.