Browsing by Author "Jiang, Zizhen"

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Design and Optimization Methodology for 3D RRAM Arrays
(2013)
Deng, Yexin
;
Chen, Hong-Yu
;
Gao, Bin
;
Yu, Shimeng
;
Wu, Shih-Chieh
3D RRAM arrays are studied at the device-and architecture-levels. The memory cell performance for a horizontal cross-point is shown experimentally to be essentially comparable to vertical pillar-around geometry. Array performances (read/write, energy, and speed) of different 3D architectures are investigated by SPICE simulation, showing horizontal stacked RRAM is superior but suffers from higher bit cost. Adopting a bi-layer pillar electrode structure is demonstrated to enlarge the array size in 3D vertical RRAM. Design guidelines are proposed for the 3D VRRAM: it shows that increasing the number of stacks of VRRAM while keeping the total bits the same, as well as scaling of feature size (F), are critical for reducing RC delay and energy consumption.
Improved Multi-level Control of RRAM Using Pulse-Train Programming
(2014-01-01)
Zhao, Liang
;
Chen, Hong-Yu
;
Wu, Shih-Chieh
;
Jiang, Zizhen
;
Yu, Shimeng
Multi-level cell (MLC) capability in RRAM is attractive for reducing the cost per bit. Based on the filamentary switching mechanisms, we propose a pulse-train programming scheme to achieve reliable and uniform MLC controls without the need of any read-verification operation. By applying the novel scheme to a 3 bit/cell RRAM device, the uniformity of resistance distribution can be improved up to 80%.