Browsing by Author "Jin, Y"

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Effects of base oxide in HfSiO/SiO2 high-k gate stacks
(2004)
Wu, WH
;
Chen, MC
;
Wang, MF
;
Hou, TH
;
Yao, LG
Electrical characteristics of HfSiO/SiO2 high-k gate stacks have been extensively explored with regard to the effects of base oxide. The flatband voltage shift in N/PMOS capacitors is independent of base oxide thickness, and the dielectric breakdown of the gate stacks is determined by base oxide. In addition, base oxide thickness has a great impact on device performance and charge trapping, presumably due to remote Coulomb scattering (RCS) in the HfSiO bulk layer and direct tunneling through the base oxide. Threshold voltage instability induced by charge trapping will be a major reliability concern for Hf-based high-k gate dielectrics in the future.
Effects of base oxide thickness and silicon composition on charge trapping in HfSiO/SiO(2) high-k gate stacks
(2005-08-01)
Wu, WH
;
Chen, MC
;
Tsui, BY
;
How, YT
;
Yao, LG
This work investigates the fundamentals of charge trapping and the effects of base oxide thickness and Si composition on charge trapping in HfSiO/SiO(2) high-k gate stacks using positive-bias temperature (PBT) stressing scheme. During the PBT stress, threshold voltage shift and saturation drain current degradation induced by charge trapping continue to grow and eventually become saturated, whereas the subthreshold swing and maximum transconductance remain unchanged. The extent of charge trapping increases with the decrease of base oxide thickness and Si composition in the HfSiO film, which can be explained by considering the channel-to-bulk tunneling time constant and the amount of neutral Hf-OH trapping centers in the HfSiO bulk layer. The power law dependence of saturation drain current degradation on the gate bias voltage indicates that charge trapping would become more significant if thin base oxide and low Si composition were employed in the further scaled HfSiO/SiO(2) high-k gate stacks.
Effects of base oxide thickness and silicon composition on charge trapping in HfSiO/SiO2 high-k gate stacks
(2005-08-01)
Wu, WH
;
Chen, MC
;
Tsui, BY
;
How, YT
;
Yao, LG
This work investigates the fundamentals of charge trapping and the effects of base oxide thickness and Si composition on charge trapping in HfSiO/SiO2 high-k gate stacks using positive-bias temperature (PBT) stressing scheme. During the PBT stress, threshold voltage shift and saturation drain current degradation induced by charge trapping continue to grow and eventually become saturated, whereas the subthreshold swing and maximum transconductance remain unchanged. The extent of charge trapping increases with the decrease of base oxide thickness and Si composition in the HfSiO film, which can be explained by considering the channel-to-bulk tunneling time constant and the amount of neutral Hf-OH trapping centers in the HfSiO bulk layer. The power law dependence of saturation drain current degradation on the gate bias voltage indicates that charge trapping would become more significant if thin base oxide and low Si composition were employed in the further scaled HfSiO/SiO2 high-k gate stacks.
HfAlON n-MOSFETs incorporating low-work function gate using ytterbium silicide
(2006-06-01)
Wu, CH
;
Hung, BF
;
Chin, A
;
Wang, SJ
;
Yen, FY
The authors have fabricated low-temperature fully silicided YbSi2-x-gated n-MOSFETs that used an HfAION gate dielectric with a 1.7-nm EOT. After a 600 degrees C rapid thermal annealing, these devices displayed an effective work function of 4.1 eV and a peak electron mobility of 180 cm(2)/V(.)s. They have additional merit of a process compatible with current very large scale integration fabrication lines.
Impact of STI on the reliability of narrow-width pMOSFETs with advanced ALD N/O gate stack
(2006-03-01)
Chung, SS
;
Yeh, CH
;
Feng, HJ
;
Lai, CS
;
Yang, JJ
For the first time, a shallow trench isolation (STI)-induced enhanced degradation in pMOSFETs for ultrathin gate oxide devices has been observed. The ID degradation is enhanced as a reduction in the gate width and the hot carrier (HC) or negative bias temperature instability (NBTI) effect. Extensive studies have been compared for atomic layer deposition (ALD)-grown and plasma-treated oxide pMOSFETs. Different temperature dependences were observed. At room temperature, hole trap is dominant for the device degradation, in which holetrap-induced V-T is significant, whereas at high temperature under NBTI stress, interface trap becomes more significant, which dominates the device ID degradation. In addition, the V-T rolloff can be modeled as a width narrowing effect specifically for STI. More importantly, the NBTI-induced interface/oxide traps are strongly related to the hydrogen and N-2 content in the gate oxide formation process. The interface trap generation is suppressed efficiently using the ALD-grown gate oxide. These results provide a valuable guideline for the understanding of the HC and NBTI reliabilities in an advanced ALD-grown gate oxide processes/devices.
The impact of STI induced reliabilities for scaled p-MOSFET in an advanced multiple oxide CMOS technology
(2004)
Chung, SS
;
Yeh, CH
;
Feng, SJ
;
Lai, CS
;
Yang, JJ
In this paper, we present new results on the width dependent hot-carrier (HC) reliabilities for shallow-trench-isolated (STI) pMOSFETs in a multiple oxide CMOS technology. For the first time, different phenomena in pMOSFET for a multiple oxide process have been observed. Extensive studies have been made for ALD grown and plasma treated oxide pMOSFETs. Experimental data shows that the drain current degradation is enhanced for a reducing gate width. For thick oxide, the I-D degradation is due to the channel length shortening, and electron trap is dominant for the device degradation. While for thin gate oxide, the I-D degradation is due to width narrowing, and hole trap is dominant, in which both electron and hole trap induced V-T shifts are significant. The degradation in thick-oxide pMOSFETs causes an increase of off-state leakage Current and an increase of DeltaV(T) in thin-oxide with reduced width.
Two-frequency C-V correction using five-element circuit model for high-k gate dielectric and ultrathin oxide
(2006-05-01)
Wu, WH
;
Tsui, BY
;
Huang, YP
;
Hsieh, FC
;
Chen, MC
A new circuit model of -five elements has been proposed for the two-frequency capacitance-voltage (C-V) correction of high-k gate dielectric and ultrathin oxide. This five-element circuit model considered the static and dynamic dielectric losses in a lossy MOS capacitor, the parasitic well/substrate resistance, and the series inductance in the cables and probing system. Each of the circuit elements could be easily extracted from the two-frequency C-V and static current-voltage (I-V) measurements if some criteria are well satisfied. In addition, this model can also be transformed into another two four-element circuit models to simplify the analysis and calculations, depending on the gate ea age current.