Browsing by Author "Jou, JY"

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A design-for-verification technique for functional pattern reduction
(2003-03-01)
Liu, CNJ
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Chen, IL
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Jou, JY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This technique reduces the number of required functional patterns by first defining conditions for hard-to-control (HTC) code in a hardware-description-language design and then using an algorithm to detect such code automatically. A second algorithm eliminates these HTC points by selecting a minimum number of nodes for control point insertion.
A divide-and-conquer-based algorithm for automatic simulation vector generation
(2004-03-01)
Yen, CC
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Jou, JY
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Chen, KC
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A logical fault model for library coherence checking
(1998-09-01)
Tung, SW
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Jou, JY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A library is the basis of modularized design now. Most operations of CAD tools are based on cell definitions in a library. In this paper, we first give a definition of a library and describe the complexity of library verification. A unified automatic test pattern generation and verification environment is then proposed. The amount of library data coherence checking is reduced to functional simulation on different views of the cells. In order to reduce the number of lest vectors and the amount of simulation time, a Port Order Fault (POF) model is proposed. Using the POF model and the sensitized path approach [1] to generate test vectors, the proposed approach could effectively reduce the complexity of the functional test vectors from O(2(n)) to O(n) for cells with n inputs. Using the POF model, the test sequence can also detect timing inconsistency under the verification environment.
A new method for constructing IP level power model based on power sensitivity
(2000-12-01)
Huang, HL
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Lin, JY
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Shen, WZ
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Jou, JY
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電子工程學系及電子研究所
As the function uf a system getting more complex. IP (Intellectual Property) reusing is the trend of system design style. Designers need to evaluate the performance and features of every candidate IP block that can be used in their design, while IP providers hope to keep the structure of tilt ir IP blocks a secret. An IP level power model is a model that takes only the primary) input statistics its parameters and does not reveal any information about the sizes of the transistors or the structure of the circuit. This paper proposes a new method for constructing power model that is suitable for IP level circuit blocks. It is a nominal point selection method, fur power models based oil power sensitivities. BS analyzing the relationship between the dynamic power consumption uf CMOS circuits and their input signal statistics, a guideline of selecting the nominal point is proposed. From our analysis. the first nominal point is selected to minimize the average Estimation error and two other nominal points are selected to minimize the maximum estimation error. Our experimental results on a number of benchmark circuits show the effectiveness of the proposed method. Average estimation accuracy within 5.78% of transistor level simulations is achieved. The proposed method can he applied to build a system level power estimation environment without revealing the contents of the IP blocks inside. Thereby. it is a promising method for IP level power model construction.
A novel approach for functional coverage measurement in HDL
(2000)
Liu, CNJ
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Chang, CY
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Jou, JY
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Lai, MC
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Juan, HM
While the coverage-driven functional verification is getting popular: a fast and convenient coverage measurement tool is necessary. In this paper, we propose a hovel approach for functional coverage measurement based on the VCD files produced by the simulators. The usage flow of the proposed dumpfile-based coverage analysis is much easier and smoother than that of existing instrumentation-based coverage tools. No pre-processing tool is required and no extra code will be inserted into the source code. Most importantly, the flexibility in choosing coverage metrics and measured code regions is increased. Only one simulation run is needed for any kind of coverage reports. By conducting some experiments on real examples: it shows very promising results in terms of the performance and the accuracy of coverage reports.
A power modeling and characterization method for macrocells using structure information
(1997)
Lin, JY
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Shen, WZ
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Jou, JY
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交大名義發表
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電子工程學系及電子研究所
To characterize a macrocell, a general method is to stare the power consumption of all possible transition events at primary inputs in the lookup tables, Though this approach is very accurate, the lookup tables could be huge for tile macrocells with many inputs, In this paper, we present a new power modeling method which rakes advantage of the structure information of macrocells and selects minimum number of primary inputs or internal nodes in a macrocell as state variables to build a state transition graph (STG). Those state variables can completely model the transitions of ail internal nodes and the primary outputs. By carefully deleting some state variables, we further introduce an incomplete power modeling technique which can simplify the STG without losing much accuracy. In addition, we exploit the properly of the compatible patterns of a macrocell to further reduce the number of edges in the corresponding STG. Experimental results show that our modeling techniques can provide SPICE-like accuracy and can reduce the size of the lookup table significantly comparing to the general approach.
A power modeling and characterization method for the CMOS standard cell library
(1996)
Lin, JY
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Shen, WZ
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Jou, JY
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交大名義發表
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電子工程學系及電子研究所
In this paper, we propose power consumption models for complex gates and transmission gates, which are extended from the model of basic gates proposed in [1]. We also describe an accurate power characterization method for CMOS standard cell libraries which accounts for the effects of input slew rare, output loading, and logic state dependencies. The characterization methodology separates the power consumption of a cell into three components, e.g., capacitive feedthrough power, short-circuit power, and dynamic power. For each component, power equation is derived from SPICE simulation results where the netlist is extracted from cell's layout. Experimental results on a set of ISCAS'85 benchmark circuits show that the power estimation based on our power modeling and characterization provides within 7% error of SPICE simulation on average while the CPU time consumed is more than two orders of magnitude less.
A structure-oriented power modeling technique for macrocells
(1999-09-01)
Lin, JY
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Shen, WZ
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Jou, JY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
To characterize the power consumption of a macrocell, a general method involves recording the power consumption of all possible input transition events in the look-up tables. However, though this approach is accurate, the size of the table becomes very large. In this paper, we propose a new power modeling technique that takes advantage of the structural information of a macrocell, In this approach, a subset of primary inputs and internal nodes in the macrocell are selected as the state variables to build a state transition graph (STG), These state variables can model the steady-state transitions completely. Moreover, by selecting the characterization patterns properly, the STG can also model the glitch power in the macrocell accurately. To further simplify the complexity of the STG, an incomplete power modeling technique is presented. Without losing much accuracy, the property of compatible patterns is exploited for a macrocell to further reduce the number of edges in the corresponding STG, Experimental results show that our modeling techniques can provide SPICE-like accuracy, while the size of the look-up table is significantly reduced.
A variable partitioning algorithm of BDD for FPGA technology mapping
(1997-10-01)
Jiang, JH
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Jou, JY
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Huang, JD
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Wei, JS
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交大名義發表
Field Programmable Gate Arrays (FPGA's) are important devices for rapid system prototyping. Roth-Karp decomposition is one of the most popular decomposition techniques for Look-Up Table (LUT)-based FPGA technology mapping. In this paper, we propose a novel algorithm based on Binary Decision Diagrams (BDD's) for selecting good lambda set variables in Roth-Karp decomposition to minimize the number of consumed configurable logic blocks (CLB's) in FPGA's. The experimental results on a set of benchmarks show that our algorithm can produce much better results than the similar works of the previous approaches [1], [4].
ALTO: An iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping
(2000-08-01)
Huang, JD
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Jou, JY
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Shen, WZ
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, we propose an iterative area/performance tradeoff algorithm for look-up table (LUT)-based held programmable gate array (FPGA) technology mapping. First, it finds an area-optimized, performance-considered initial network by a modified area optimization technique. Then, an iterative algorithm consisting of several resynthesizing techniques is applied to trade the area for the performance in the network gracefully. Experimental results show that this approach can efficiently provide a complete set of mapping solutions from the area-optimized one to the performance-optimize one for the given design. Furthermore, these two extreme solutions produced by our algorithm outperform the results provided by most existing algorithms. Therefore, our algorithm is very useful for the timing-driven, LUT-based FPGA synthesis.
An automatic controller extractor for HDL descriptions at the RTL
(2000-07-01)
Liu, CNJ
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Jou, JY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Extracting controlling finite-state machines can significantly reduce state space and thereby speed functional verification. The controller extraction algorithm uses an approach that frees it from restrictions on HDL code writing style.
An automatic interconnection rectification technique for SoC design integration
(2003)
Wang, CY
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Tung, SW
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Jou, JY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents an automatic interconnection rectification (AIR) technique to correct the misplaced interconnection occurred in the integration of a SoC design automatically. The experimental results show that the AIR can correct the misplaced interconnection and therefore accelerates the integration verification of a SoC design.
An automorphic approach to verification pattern generation for SoC design verification using port-order fault model
(2002-10-01)
Wang, CY
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Tung, SW
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Jou, JY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Embedded cores are being increasingly used in the design of large system-on-a-chip (SoC). Because of the high complexity of SoC, the design verification is a challenge for system integrators. To reduce the verification complexity, the port-order fault (POF) model was proposed. It has been used for verifying core-based designs and the corresponding verification pattern generation has been developed. Here, the authors present an automorphic technique to improve the efficiency of the automatic verification pattern generation (AVPG) for SoC design verification based on the POF model. On average, the size of pattern sets obtained on the ISCAS-85 and MCNC benchmarks are 45 % smaller and the run time decreases 16 % as compared with the previous results of AVPG.
An efficient approach for error diagnosis in HDL design
(2003)
Shi, CH
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Jou, JY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The growing of the modem design complexity leads the design error diagnosis to be a challenge for designers. In this paper, we propose an efficient approach for design error diagnosis automatically for designs in HDL. This approach can handle multiple errors occurring in a HDL design simultaneously with only one test case by analyzing the simulation outputs of the incorrect implementation. Furthermore, this approach reduces the error space by eliminating those statements that have no or lower possibility to become the error sources with retaining at least one error source in it. Hence, the effort spent on the debugging process can be greatly reduced.
An efficient approach for hierarchical submodule extraction
(2004)
Lin, YW
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Jou, JY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The growth of modem IC design complexity leads the consistency check and design verification during every level in design flow to be an important and challenged issue. In this paper, we propose an efficient approach to rebuild the hierarchical level from low level circuits. Our approach is based on the structure equivalent expansion algorithm to find repeated submodules in every circuit level to reconstruct circuit hierarchy. Without any addition library information, our approach is quite efficient in both time and space complexities by using only flatten netlists. The experiments on many real circuits containing combinational, sequential, and memory circuits show that our approach can rebuild most circuit hierarchical levels and also reduce the verification effort of the circuits.
An efficient design-for-verification technique for HDLs
(2001)
Liu, CNJ
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Chen, IL
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Jou, JY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Due to the high complexity of modern circuit designs, verification has become the major bottleneck of the entire design process. There is an emerging need for a practical solution to reduce the verification time. In manufacturing test, a well-known technique, "design-for-testability'', is often used to reduce the testing time. By inserting some extra circuits on the hard-to-test points, the testability can be improved and the testing time can be reduced. In this paper, we apply the similar idea to functional verification and propose an efficient "design-for-verification" (DFV) technique to help users reduce the verification time. The conditions for hard-to-control (HTC) codes in a HDL design are clearly defined, and an efficient algorithm to detect them automatically is proposed. Besides the HTC detection, we also propose an algorithm that can eliminate those HTC points with minimum number of DFV points. By the help of those DFV points, the number of required test patterns to reach the same coverage can be greatly reduced especially for deep-sequential designs.
An efficient heterogeneous tree multiplexer synthesis technique
(2005-10-01)
Huang, HW
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Wang, CY
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Jou, JY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, a novel strategy for designing the heterogeneous tree multiplexer is proposed. The authors build the multiplexer delay model by curve fitting and then formulate the heterogeneous tree multiplexer design problem as a special type of optimization problem called mixed-integer nonlinear programming (MINLP). A new design parameter, the switch size in each stage, is introduced to improve the speed of the heterogeneous tree multiplexer. The proposed strategy can determine the multiplexer architecture and the switch size in each stage simultaneously. Three optimization methods are provided to synthesize the heterogeneous tree multiplexer according to the design specifications.
An efficient IP-Level power model for complex digital circuits
(2003)
Hsu, CY
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Liu, CNJ
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Jou, JY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, we propose an efficient IP-Level power model with a small lookup table for complex CMOS circuits. The table has only one dimension that maps the zero-delay charging and discharging capacitance into the real power consumption of pattern pairs but still has high accuracy. In order to improve the efficiency of the characterization process, the Monte Carlo approach is used during the estimation of the average power to skip the samples that will not increase the accuracy too much. The experimental result shows the table sizes are only up to 107 entries for ISCAS'85 benchmark circuits and the estimation error is only 2.99% on average using the lookup table.
An efficient logic extraction algorithm using partitioning and circuit encoding
(2004)
Huang, L
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Jiang, TY
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Jou, JY
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Huang, HL
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電子工程學系及電子研究所
Nowadays, finding subcircuits in a larger circuit is primarily solved by using various heuristics based on graph isomorphism. These approaches are addressed on identify g one specific subcircuit at each time and may take numerous runs if many subcircuits need to be extracted. Therefore, they are not quite suitable for converting the whole circuit represented at transistor-level to a gate-level netlist. We present a logic extraction approach based on dc-connected component (DCC) partition and modified circuit-encoding algorithm to extract all kinds of subscircuits from the input circuit concurrently such that we can. map each subcircuit represented as transistor level netlist to its corresponding logic gate. This mapping relation can be exploited to speed up the simulation of large circuits. Experiments on several real circuits, including sequential logic ones and combination logic ones, show the near-linear performance in run time and memory usage.
An efficient power model for IP-level complex designs
(2003-08-01)
Hsu, CY
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Liu, CNJ
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Jou, JY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, we propose an efficient IP-Level power model with a small lookup table for complex CMOS circuits. The table has only one dimension that maps the zero-delay charging and discharging capacitance (CDC) into the real power consumption of pattern pairs but still has high accuracy. In order to reduce the table size, we collect those pattern pairs with similar CDC values to be a group and only set an entry in the lookup table for each group. The proposed dynamic grouping process can automatically increase the entries of the lookup tables to cover the current CDC distribution of designs during the power characterization process. In order to improve the efficiency of characterization process, the Monte Carlo approach is used during the estimation for the average power of each group to skip the samples that will not increase the accuracy too much. After the power model of a circuit is built, the average power consumption for any test sequence can be estimated easily. The experimental result shows that the table sizes are only up to 107 entries for ISCAS'85 benchmark circuits and the estimation error is only 2.99% on average using this lookup table.