Browsing by Author "Jou, S. -J."

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Design techniques for high-speed multirate multistage FIR digital filters
(2006-10-01)
Lin, M. -C.
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Chen, H. -Y.
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Jou, S. -J.
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents architecture design techniques for implementing both single-rate and multirate high-speed finite impulse response (FIR) digital filters, with emphasis on the multirate multistage interpolated FIR (IFIR) digital filters. Well-known techniques to achieve high-speed and low-power applications for the single-rate digital FIR architecture are summarized, followed by the introduction of variable filter order selection, optimal filter decomposition, memory-saving and mirror symmetric filter pairs techniques which offer further gains in both performance and complexity reduction for the multirate multistage digital FIR architecture. A filter design example with TSMC 0.25 mu m standard cell for 64-QAM baseband demodulator shows that the area is reduced by 39% for low-complexity application. Moreover, for high-speed application, the chip can operate at 714 MHz. Finally, a designed decimator which is used in the CDMA cellular shows that the area is reduced by 70% as compared with conventional approach.
High throughput concurrent lookahead adaptive decision feedback equaliser
(2012-01-01)
Lin, Y. -C.
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Jou, S. -J.
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Shiue, M. -T.
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A time-domain adaptive decision feedback equaliser (ADFE) for multi-gigabit wire-line 2-pulse amplitude modulation (PAM) communication systems is proposed. The throughput rate of a conventional ADFE is limited by the loops in the circuit. This investigation develops two methods for breaking or virtually breaking these loops. The first is the method of batch mode coefficient updating (BMCU), and the second is the concurrent lookahead (CLA) method. Since the loops are broken or virtually broken, a pipeline and/or a parallel method can be applied to design a throughput-rate-unlimited ADFE. The results of a simulation of the 10GBASE-S system reveal that the proposed BMCU-based CLA ADFE has the same average signal-to-noise ratio (SNR) as the original sequential ADFE for multi-mode fibres of length 30-90 m.
Near-threshold all-digital PLL with dynamic voltage scaling power management
(2016-01-21)
Chang, C. -W.
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Chang, K. -Y.
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Chu, Y. -H.
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Jou, S. -J.
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電子工程學系及電子研究所
A near-threshold all-digital phase-locked loop (ADPLL) with a power management unit (PMU) is presented to make the proposed ADPLL work reliably across variations and power consumption as well is reduced. When operated under near-threshold condition from 0.52 to 0.58 V V-DD, the gated digitally controlled oscillator frequency range is from 90.8 to 245.7 MHz. When the ADPLL is operated at 0.52 V V-DD, a lock-in time of 9.5 mu s at 100 MHz output clock frequency is measured with an rms period jitter of 0.17% UI. With the PMU, the ADPLL power reduction at 130 MHz output frequency is 39% and the buck converter power consumption is nearly 30 mu W. Consequently, the proposed ADPLL with PMU is suitable to event-driven or low-voltage applications.