Browsing by Author "Jou, SJ"

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A 12.5 Gbps CMOS input sampler for serial link receiver front end
(2005)
Jou, SJ
;
Lin, CH
;
Wang, YI
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a high-speed CMOS input sampler used for serial link receiver front end. The input sampler consists of a comparator, a SR latch and a D flip-flop. Because a parallel architecture is used for the 1:8 demultiplexing and 3x oversamphing is utilized for data recovery, there are 24 input samplers in receiver front end. These input samplers are implemented in TSMC0.18um. 1P6M process with area of 252*162 um(2). The circuits can operate at maximum input data rate of 12.7 Gbps with differential signal of 300 mV using supply voltage of 1.8V.
Multi-gigabit pre-emphasis design and analysis for serial link
(2005-10-01)
Lin, CH
;
Tsai, CH
;
Chen, CN
;
Jou, SJ
;
電子工程學系及電子研究所
In this paper, a multi-Gbps pre-emphasis design methodology and circuits for a 4/2 Pulse Amplitude Modulation (PAM) transmitter of high-speed data serial link over cable are proposed. Theoretically analysis of the total frequency response including pre-emphasis, package, cable loss and termination are first carried out. In order to gain higher data rates without increasing of symbol rate, we use 4 PAM in our system. Then, we propose a pre-emphasis architecture and algorithm that can enlarge the high frequency response so the overall frequency response in the receiver side is uniform within the desired frequency range. The overall circuit is implemented in TSMC 0.18 mu m 1P6M 1.8 V CMOS process. A test chip of this transmitter with pre-emphasis, PLL circuit and on-chip termination resistors is implemented by full custom flow to verify the design methodology. The measurement results of 10/5 Gbps (4/2 PAM) are carried out over 5 meter (m) long cable and is in agreement with our analysis and Simulation results.
Multi-gigabit serial link transmitter- off-chip and on-chip
(2005)
Jou, SJ
;
Lin, CH
;
Chen, CN
;
Wang, YJ
;
Hsiao, JY
Multi-Gbps serial link transmitter for both off-chip and on-chip transmission are presented. For off-chip transmission, a new pre-emphasis design methodology and circuits for a 4/2 PAM transmitter over cable are proposed. A test chip of transmitter with pre-emphasis, PLL circuit and on-chip termination resistors is implemented using tsmc 0.18 urn CMOS process. The measurement results of 1015 Gbps (4/2 PAM) are carried out over 5 meter (m) long cable and is in agreement with our analysis and simulation results. For on-chip transmission, SerDes based serial link architecture is used in on-chip application. Using tsmc 0.13 um CMOS process, the operation speed and power consumption are 5 Gbps and 3.2 mW respectively with the interconnect area is half of parallel architecture.