Browsing by Author "Jou, Shyh-Jye Jerry"

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A 75-Gb/s/mm(2) and Energy-Efficient LDPC Decoder Based on a Reduced Complexity Second Minimum Approximation Min-Sum Algorithm
(2020-04-01)
Lopez, Henry
;
Chan, Hsun-Wei
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Chiu, Kang-Lun
;
Tsai, Pei-Yun
;
Jou, Shyh-Jye Jerry
This article presents a high-throughput and low-routing complexity low-density parity check (LDPC) decoder design based on a novel second minimum approximation min-sum (SAMS) algorithm. The routing congestion is mitigated by reducing the required interconnections in the critical path of the routing network. The implementation and postlayout results with 28-nm 1P9M CMOS process show that the proposed design can achieve a throughput of 10.5 Gb/s for a millimeter-wave 60-GHz baseband system while satisfying the low bit error rate (BER) requirements (10(-7)). The proposed design reduces the wiring in the routing network by 21% and improves the area by 12% compared to the conventional min-sum (MS) and normalized MS (NMS) algorithm. Additional hardware optimizations are obtained by considering the internal message passing resolution based on the BER and signal-to-noise ratio (SNR) requirements for a practical baseband system. The power consumption is efficiently reduced by the employment of a shared address generator that exploits the degree of parallelism to reduce the switching activity on a group of memory elements. The LDPC decoder is implemented with a core area of 0.14 mm(2), power consumption of 81 mW at 312.5 MHz, and the area and power efficiency of 75 Gb/s/mm(2) and 10.2 pJ/bit, respectively.
Design of Downlink Synchronization for Millimeter Wave Cellular System Based on Multipath Division Multiple Access
(2020-09-01)
Chiu, Kang-Lun
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Shen, Pai-Hsiang
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Lin, Bing-Ru
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Hsiao, Wei-Han
;
Jou, Shyh-Jye Jerry
This work focuses on the design of downlink receiver for future generation cellular systems. In the multipath division multiple access (MDMA) system, the initial synchronization process includes timing and carrier frequency synchronization as well as home cell search. For the proposed system, the user data is transmitted in time domain and the cell search is based on control signals transmitted in frequency domain simultaneously. Firstly, this paper presents a novel architecture for the joint detection and estimation of both the coarse symbol boundary and the fractional carrier frequency offset based on cyclic prefix in time domain. Secondly, a robust integer carrier frequency offset detection is performed with the primary control tone in frequency domain. Moreover, the position of the secondary control tones is used to obtain the cell ID. Finally, the preamble sequence carried by the secondary control tones is used to detect frame header through differential detection. The simulation results show the proposed synchronization algorithms can achieve detection failure rate less than 1% and the normalized residual carrier frequency offset is less than 5% under the interference of user data. Furthermore, a hardware design targeted at 200 Mbps per-user data rate is realized with memory arbiter to share memory.