Browsing by Author "Jou, YN"

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A physical model for the correlation between holding voltage and holding current in epitaxial CMOS latch-up
(1998-08-01)
Chen, MJ
;
Lee, HS
;
Chen, JH
;
Hou, CS
;
Lin, CS
A new physical model concerning the holding points for latch-up in epitaxial CMOS structures is established by combining the lateral p-i-n high level injection and the vertical BJT base push-out formula. The model matches adequately the correlation between holding voltage and holding current extensively measured from different combinations of temperatures, epitaxial layer thicknesses, and anode-to-cathode spacings, This is also the case for the two-dimensional device simulations. A quantitative analysis based on the model consistently judges the crucial role of the vertical BJT base push-out width in producing the observed correlation. The potential merits of the model in extended applications are outlined.
Back-gate forward bias method for low-voltage CMOS digital circuits
(1996-06-01)
Chen, MJ
;
Ho, JS
;
Huang, TH
;
Yang, CH
;
Jou, YN
The back-gate forward bias method suitable for present standard hulk CMOS processes has been promoted for low-voltage digital circuit application, A CMOS inverter employing the method has experimentally exhibited the ability of electrically adjusting the transition region of the de voltage transfer characteristics. Transient measurement has further shown that the inverter with a back-gate forward bias of 0.4 V can operate at low supply voltages down to 0.6 V without significant loss in switching speed, Guidelines for ensuring proper implementation of tile method in a bulk CMOS process has been set up against latch-up, parasitic bipolar, impact ionization, and stand-by current, Following these guidelines, a cost-effective low-power, low-voltage, high-density mixed-mode CMOS analog/digital integrated circuits chip with both reasonable speed and improved precision has been projected for the first time.