Browsing by Author "Jou Shyh-Jye"

Now showing 1 - 13 of 13

DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL
(2011-06-02)
Chuang Ching-Te
;
Yang Hao-I
;
Lin Jihi-Yu
;
Yang Shyh-Chyi
;
Tu Ming-Hsien
A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line.
Disturb-free static random access memory cell
(2012-09-04)
Chuang Ching-Te
;
Yang Hao-I
;
Lin Jihi-Yu
;
Yang Shyh-Chyi
;
Tu Ming-Hsien
A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line.
Oscillato based on a 6T SRAM for measuring the bias temperature instability
(2014-08-12)
Chuang Ching-Te
;
Jou Shyh-Jye
;
Hwang Wei
;
Tsai Ming-Chien
;
Lin Yi-Wei
The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately.
Oscillator based on a 6T SRAM for measuring the Bias Temperature Instability
(2013-08-29)
Chuang Ching-Te
;
Jou Shyh-Jye
;
Hwang Wei
;
Tsai Ming-Chien
;
Lin Yi-Wei
The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately.
SINGLE-ENDED SRAM WITH CROSS-POINT DATA-AWARE WRITE OPERATION
(2013-08-01)
Jou Shyh-Jye
;
Lin Jhih-Yu
;
Chuang Ching-Te
;
Tu Ming-Hsien
;
Chiu Yi-Wei
A single-ended SRAM including at least one memory cell and a third switch is provided. The memory cell includes a data-latching unit, a first switch, a second switch and a data-transferring unit. The data-latching unit is configured for latching the received input data and provides a storage data and the inverse data of the storage data. The first switch transfers a reference data to the data-latching unit according to a first word-line signal. The second switch transfers the reference data to the data-latching unit according to a second word-line signal. The data-transferring unit decides whether or not to transfer the reference data to the bit-line according to the storage data and a control signal. The third switch receives the reference data and the control signal and transfers the reference data to the first switch, the second switch and the data-transferring unit according to the control signal.
Single-ended SRAM with cross-point data-aware write operation
(2014-04-08)
Jou Shyh-Jye
;
Lin Jhih-Yu
;
Chuang Ching-Te
;
Tu Ming-Hsien
;
Chiu Yi-Wei
A single-ended SRAM including at least one memory cell and a third switch is provided. The memory cell includes a data-latching unit, a first switch, a second switch and a data-transferring unit. The data-latching unit is configured for latching the received input data and provides a storage data and the inverse data of the storage data. The first switch transfers a reference data to the data-latching unit according to a first word-line signal. The second switch transfers the reference data to the data-latching unit according to a second word-line signal. The data-transferring unit decides whether or not to transfer the reference data to the bit-line according to the storage data and a control signal. The third switch receives the reference data and the control signal and transfers the reference data to the first switch, the second switch and the data-transferring unit according to the control signal.
SRAM based on 6 transistor structure including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor
(2013-08-29)
CHUANG Ching-Te
;
Jou Shyh-Jye
;
Hwang Wei
;
Lin Yi-Wei
;
Tsai Ming-Chien
The present invention provides a 6T SRAM including a first inverter, a second inverter, a first pass-gate transistor, and a second pass-gate transistor. The first inverter zs a first pull-up transistor and a first pull-down transistor. The second inverter includes a second pull-up transistor and a second pull-down transistor. The gate of the second pull-up transistor is coupled with the gate of the second pull-down transistor, and the drain of the second pull-up transistor is coupled with the drain of the second pull-down transistor. The SRAM can measure the trip voltage, the read disturb voltage, and the write margin by controlling the first bit line, the second bit line, the GND, the first word line, and the voltage source without changing of the physic parameter of the SRAM.
Static memory and memory cell thereof
(2014-09-16)
Jou Shyh-Jye
;
Tu Ming-Hsien
;
Hu Yu-Hao
;
Chuang Ching-Te
;
Chiu Yi-Wei
A static memory and a static memory cell are provided. The static memory cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first switch, a second switch, a third switch, a first pull-down switch, and a second pull-down switch. When a data writing operation is performed, the latching capability of the latch circuit constituted by the first to the sixth transistors is disabled by turning off the second transistor or the fifth transistor, so that the speed of the data writing operation is increased and the data writing performance is improved. The first switch and the second switch provide a path for reading or writing data, and the third switch is coupled to a bit line for receiving data from or transmitting data to the bit line.
STATIC MEMORY CELL
(2015-06-11)
Chuang Ching-Te
;
Chang Chih-Hao
;
Chung Chao-Kuei
;
Lu Chien-Yu
;
Jou Shyh-Jye
A static memory cell is provided. The static memory cell includes a data latch circuit and a voltage provider. The data latch circuit is configured to store a bit data. The data latch circuit has a first inverter and a second inverter, and the first inverter and the second inverter are coupled to each other. The first inverter and the second inverter respectively receive a first voltage and a second voltage as power voltages. The voltage provider provides the first voltage and the second voltage to the data latch circuit. When the bit data is written to the data latch circuit, the voltage provider adjusts a voltage value of one of the first and second voltages according to the bit data.
Static random access memory with data controlled power supply
(2012-11-27)
Chuang Ching-Te
;
Yang Hao-I
;
Hsia Mao-Chih
;
Lin Yung-Wei
;
Lu Chien-Yu
A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.
STATIC RANDOM ACCESS MEMORY WITH DATA CONTROLLED POWER SUPPLY
(2012-01-12)
Chuang Ching-Te
;
Yang Hao-I
;
Hsia Mao-Chih
;
Lin Yung-Wei
;
Lu Chien-Yu
A static random access memory with data controlled power supply, which comprises a memory cell circuit and at least one Write-assist circuit, for providing power to the memory cell circuit according to data to be written to the memory cell circuit.
Static random access memory with ripple bit lines/search lines for improving current leakage/variation tolerance and density/performance
(2014-07-08)
Chuang Ching-Te
;
Yang Hao-I
;
Lu Chien-Yu
;
Chen Chien-Hen
;
Chang Chi-Shin
A static random access memory includes a pre-charger, a first cell column array/peripheral circuit, and a first ripple buffer. The pre-charger is connected to a first local bit line in order to pre-charge the first local bit line. The first cell column array/peripheral circuit is connected to the first local bit line and has a plurality of cells for temporarily storing data. The cells are connected to the first local bit line. The first ripple buffer is connected to the first local bit line and a second local bit line in order to send the data from the first local bit line to the second local bit line.
Threshold voltage measurement device
(2013-11-12)
Chuang Ching-Te
;
Jou Shyh-Jye
;
Lin Geng-Cing
;
Wang Shao-Cheng
;
Lin Yi-Wei
A threshold voltage measurement device is disclosed. The device is coupled to a 6T SRAM. The SRAM comprises two inverters each coupled to a FET. Power terminals of one inverter are in a floating state; the drain and source of the FET coupled to the inverter are short-circuited. Two voltage selectors, a resistor, an amplifier and the SRAM are connected in a negative feedback way. Different bias voltages are applied to the SRAM for measuring threshold voltages of two FETs of the other inverter and the FET coupled to the other inverter. The present invention uses a single circuit to measure the threshold voltages of the three FETs without changing the physical structure of the SRAM. Thereby is accelerated the measurement and decreased the cost of the fabrication process and measurement instruments.