Browsing by Author "Jui, Ping-Chang"

Now showing 1 - 5 of 5

A Unitized Charging and Discharging Smart Battery Management System
(2013-01-01)
Wey, Chin-Long
;
Jui, Ping-Chang
;
電機工程學系
;
Department of Electrical and Computer Engineering
Rechargeable batteries are widely used in many portable electronic products and consumer devices. This paper presents a unitized charging and discharging battery management system (UCD BMS) with distributed battery units allowing some battery units to be discharged their energy running the vehicle, while some other units are charged from the energy harvesting with photovoltaics or other technologies. The proposed UCD BMS comprises of a smart battery module, a programmable battery management (PBM) module, a charging module, and a discharging module. The PBM module contains a control circuitry and a programmable path array (PPA) module which is realized by switching circuits. The control circuitry turns on and off the corresponding switches in the PPA module forming two paths: (1) battery path; and (2) charging (discharging) path. The smart battery charger (load) included in the charging (discharging) path is then connected to the battery path which includes the smart battery units to be charged (discharged). The proposed PBM provides various output voltages so that the smart battery module is used more flexibly and enhances the utilization rate of the discharge energy, improving the overall power efficacy of the smart battery module. The PBM can also be applied for battery balancing and fault-tolerant BMS design.
Efficient Algorithm and Fast Hardware Implementation for Multiply-by-(1+2(k))
(2015-04-01)
Wey, Chin-Long
;
Jui, Ping-Chang
;
Shiue, Muh-Tian
;
電機資訊學士班
;
Undergraduate Honors Program of Electrical Engineering and Computer Science
A constant multiplier performs a multiplication of a data-input with a constant value. Constant multipliers are essential components in various types of arithmetic circuits, such as filters in digital signal processor (DSP) units, and they are prevalent in modern VLSI designs. This study presents an efficient algorithm and fast hardware implementation for performing multiply-by-(1+2(k)) operation with additions. No multiplications are needed. The value of (1+2(k))N can be computed by adding N to its k-bit left-shifted value 2(k)N. The additions can be performed by the full-adder-based (FA-based) ripple carry adder (RCA) for simple architecture. This paper introduces the unit cells for additions (UCAs) to construct the UCA-based RCA which achieves 35% faster than the FA-based RCA in speed performance. Further, in order to improve the speed performance, a simple and modular hybrid adder is presented with the proposed UCA concept, where the carry lookahead adder (CLA) as a module and many of the CLA modules are serially connected in a fashion similar to the RCA. Results show that the hybrid adder significantly improves the speed performance.
Efficient Multiply-by-3 and Divide-by-3 Algorithms and Their Fast Hardware Implementation
(2014-02-01)
Wey, Chin-Long
;
Jui, Ping-Chang
;
Sung, Gang-Neng
;
電機工程學系
;
Department of Electrical and Computer Engineering
This study presents efficient algorithms for performing multiply-by-3 (3N) and divide-by-3 (N/3) operations with the additions and subtractions, respectively. No multiplications and divisions are needed. Full adder (FA) and full subtractor (FS) can be implemented to realize the N3 and N/3 operations, respectively. For fast hardware implementation, this paper introduces two basic cells UCA and UCS for 3N and N/3 operations, respectively. For 3N operation, the UCA-based ripple carry adder (RCA) and carry lookahead adder (CLA) designs are proposed and their speed performances are estimated based on the delay data of standard cell library in TSMC 0.18 mu m CMOS process. Results show that the 16-bit UCA-based RCA is about 3 times faster than the conventional FA-based RCA and even 25% faster than the FA-based CLA. The proposed 16-bit and 64-bit UCA-based CLAs are 62% and 36% faster than the conventional FA-based CLAs, respectively. For N/3 operations, ripple borrow subtractor (RBS) is also presented. The 16-bit UCS-based RBS is about 15.5% faster than the 16-bit FS-based RBS.
Enhancement of Controller Area Network (CAN) Bus Arbitration Mechanism
(2013-01-01)
Wey, Chin-Long
;
Hsu, Chung-Hsien
;
Chang, Kun-Chun
;
Jui, Ping-Chang
;
電機工程學系
FlexRay protocol includes a static time-triggered and a dynamic event-triggered segment, where the static segment enabling a guaranteed real-time transmission of critical data, while the dynamic segment (optional) for low-priority and event-triggered data. FlexRay is operated in a synchronous fashion. Based on the CAN (Controller Area Network) bus arbitration mechanism, this study takes the most significant bit (MSB), D10, of the identifier to assign the messages to be either static-like or dynamic-like, where the static-like type has higher priority than the dynamic-like type. Both types are operated in an asynchronous fashion as the conventional CAN protocol. With the designers\' experience with good schedulability, the above assignment can ensure that all critical messages be sent out before their deadline and no one message type hugs the bus. However, the salient feature is achieved at the cost of losing one bit for the identifier.
Low-Cost Parallel FFT Processors with Conflict-Free ROM-Based Twiddle Factor Generator for DVB-T2 Applications1
(2013)
Jui, Ping-Chang
;
Wey, Chin-Long
;
Shiue, Muh-Tian
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a conflict-free ROM addressing scheme for generating the TF tables. Basically, the conventional (N/2)-words ROM table for the Radix-2 Memory-Based FFT (MBFFT) processor with single process element (PE) is equally partitioned into 2(p) sub-tables allowing all 2(p) PEs to simultaneously access the twiddle factors without causing any conflict. This study presents the use of MBFFT processor with 4 parallel PEs. Result show that the proposed scheme can reduce the chip area of DVB-T2 applications by 18.85%. The hardware reduction is of significance.