Browsing by Author "Jung, Jinwook"

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DATC RDF-2019: Towards a Complete Academic Reference Design Flow
(2019-01-01)
Chen, Jianli
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Jiang, Iris Hui-Ru
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Jung, Jinwook
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Kahng, Andrew B.
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Kravets, Victor N.
We describe a new RDF-2019 release of the IEEE CEDA DATC Robust Design Flow (RDF). RDF-2019 enhances the DATC RDF to span the entire RTL-to-GDS IC implementation flow, from logic synthesis to detailed routing. The new release represents a significant revision of the previously-reported RDF-2018 flow. Noteworthy vertical extensions include addition of logic synthesis starting from pure behavioral RTL Verilog RTL; floorplanning that includes initial DEF creation, I/O placement and PDN layout generation; and clock tree synthesis between placement legalization and global routing. A number of horizontal extensions to RDF are achieved by incorporating additional tool options at the static timing analysis, global placement, gate sizing, and detailed routing stages of the flow. Further, for the first time, multiple open-source realizations of the entire RDF tool chain are available. Last, RDF-2019 provides significantly enhanced support of and interoperability with industry-standard tools and design formats (LEF/DEF, SPEF, Liberty, SDC, etc.). We illustrate the configuration and use of RDF-2019, with example results on open as well as commercial design enablements.
DATC RDF: An Academic Flow from Logic Synthesis to Detailed Routing
(2018-01-01)
Jung, Jinwook
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Jiang, Iris Hui-Ru
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Chen, Jianli
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Lin, Shih-Ting
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Li, Yih-Lang
In this paper, we present DATC Robust Design Flow (RDF) from logic synthesis to detailed routing. We further include detailed placement and detailed routing tools based on recent EDA research contests. We also demonstrate RDF in a scalable cloud infrastructure. Design methodology and cross-stage optimization research can be conducted via RDF.
DATC RDF: Robust Design Flow Database
(2017-01-01)
Jung, Jinwook
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Lee, Pei-Yu
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Wu, Yan-Shiun
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Darav, Nima Karimpour
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Jiang, Iris Hui-Ru
In this paper, we present DATC Robust Design Flow Database covering the stages from logic synthesis to physical design [1]. Based on this database, design flow and cross-stage optimization research can be conducted via various EDA tools developed from academia.
OpenDesign Flow Database: The Infrastructure for VLSI Design and Design Automation Research
(2016)
Jung, Jinwook
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Jiang, Iris Hui-Ru
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Nam, Gi-Joon
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Kravets, Victor N.
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Behjat, Laleh
Recently, there have been a slew of design automation contests and released benchmarks. ISPD place & route contests, DAC placement contests, timing analysis contests at TAU and CAD contests at ICCAD are good examples in the past and more of new contests are planned in the upcoming conferences. These are interesting and important events that stimulate the research of the target problems and advance the cutting edge technologies. Nevertheless, most contests focus only on the point tool problems instead of addressing the design flow or co-optimization among design tools. OpenDesign Flow Database platform is developed to direct attentions to the overall design flow from logic synthesis to physical design optimization [1]. The goals are to provide an academic reference design flow based on past CAD contest results, the database for design benchmarks and point tool libraries, and standard design input/output formats to build a customized design flow by composing point tool libraries.
OWARU: Free Space-Aware Timing-Driven Incremental Placement
(2016)
Jung, Jinwook
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Nam, Gi-Joon
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Reddy, Lakshmi
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Jiang, Iris Hui-Ru
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Shin, Youngsoo
This paper proposes a powerful new technique called "OWARU"(1) that re-places and re-sizes multiple gates simultaneously to improve the most critical paths of a design. In essence, it is an incremental timing-driven placement technique integrated with gate sizing optimization that runs in conjunction with static timing analysis to guarantee a WYSIWYG (2) property. The OWARU technique offers several key advantages over previous techniques such as geometrical path straightening via the Bezier-curve algorithm, free space awareness to guarantee a legal placement solution, and an accurate true timing mode. The Bezier-curve geometric smoothing algorithm is extended with new anchor placement techniques to further improve the path placement. Free space aware placement algorithm is further enhanced with multiple gate optimization. The preliminary results are promising. We applied the OWARU technique at the end of industrial strength physical synthesis optimization on high performance microprocessor designs. The technique was extremely effective in improving the most critical path of the tested designs. On timing critical paths that were not fully closed from the previous physical synthesis optimization, the WS (worst slack) is improved by 5.3% of the total clock period and the TNS (total negative slack) improved by 91.3% on average.