Browsing by Author "KER, MD"

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A NEW ON-CHIP ESD PROTECTION CIRCUIT WITH DUAL PARASITIC SCR STRUCTURES FOR CMOS VLSI
(1992-03-01)
WU, CY
;
KER, MD
;
LEE, CY
;
KO, J
;
電控工程研究所
A new CMOS on-chip electrostatic discharge (ESD) protection circuit which consists of dual parasitic SCR structures is proposed and investigated. Experimental results show that with a small layout area of 8800-mu-m2, the protection circuit can successfully perform negative and positive ESD protection with failure thresholds greater than +/- 1 and +/- 10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. The low ESD trigger voltages in both SCR's can be readily achieved through proper circuit design and without involving device or junction breakdown. The input capacitance of the proposed protection circuit is very low and no diffusion resistor between I/O pad and internal circuits is required, so it is suitable for high-speed applications. Moreover, this ESD protection circuit is fully process compatible with CMOS technologies.
AN ON-CHIP ESD PROTECTION CIRCUIT WITH COMPLEMENTARY SCR STRUCTURES FOR SUBMICRON CMOS ICS
(1994)
KER, MD
;
WU, CY
;
JIANG, HC
;
LEE, CY
;
KO, J
CMOS ON-CHIP ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT USING 4-SCR STRUCTURES WITH LOW ESD-TRIGGER VOLTAGE
(1994-01-01)
KER, MD
;
WU, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A robust CMOS on-chip ESD protection circuit is proposed, which consists of four parasitic lateral SCR devices with low ESD trigger voltages to protect NMOS and PMOS devices of the internal circuits against the ESD pulses with both positive and negative polarities with respect to either VDD or VSS(GND) nodes. For each ESD stress with positive or negative polarity, there is an efficient and direct shunt path generated by the SCR low-impedance latching state to quickly bypass the ESD current. Thus, this four-SCR ESD protection circuit can perform very efficient protection in a small layout area. Since there is no diffusion or polysilicon resistor in the proposed ESD protection circuit, the RC delay between each U/O pad and its internal circuits is very low and high-speed applications are feasible. The experimental results show that this four-SCR protection circuit can successfully perform very effective protection against ESD damage. Moreover, the proposed ESD protection circuit is fully process-compatible with n-well or p-well CMOS and BiCMOS technologies.
Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's
(1995)
KER, MD
;
WU, CY
;
CHANG, HH
;
CHENG, T
;
WU, TS
COMPLEMENTARY-SCR ESD PROTECTION CIRCUIT WITH INTERDIGITATED FINGER-TYPE LAYOUT FOR INPUT PADS OF SUBMICRON CMOS ICS
(1995-07-01)
KER, MD
;
WU, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new ESD protection circuit with complementary SCR structures and junction diodes is proposed, This complementary-SCR ESD protection circuit with interdigitated finger-type layout has been successfully fabricated and verified in a 0.6-mu m CMOS SRAM technology with LDD process, The proposed ESD protection circuit can be free of VDD-to-VSS latchup issue under 5-V VDD operation by means of base-emitter shorting method, To compensate the degradation on latching capability of lateral SCR devices in the ESD protection circuit caused by base-emitter shorting method, the p-well to p-well spacing of lateral BJT's in the lateral SCR devices is reduced to lower its ESD-trigger voltage and to enhance turn-on speed of positive-feedback regeneration in the lateral SCR devices. This ESD protection circuit can perform high ESD failure threshold in a small layout area, so it is very suitable for submicron CMOS VLSI/ULSI's in high-pin-count or high-density applications.
MODELING THE POSITIVE-FEEDBACK REGENERATIVE PROCESS OF CMOS LATCHUP BY A POSITIVE TRANSIENT POLE METHOD .1. THEORETICAL DERIVATION
(1995-06-01)
KER, MD
;
WU, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel method to characterize the mechanism of positive-feedback regeneration in a p-n-p-n structure during CMOS latchup transition is developed, It is based on the derived time-varying transient poles in large-signal base-emitter voltages of the lumped equivalent circuit of a p-n-p-n structure, Through calculating the time-varying transient poles during CMOS latchup transition, it is found that there exists a transient pole to change from negative to positive and then this pole changes to negative again, A p-n-p-n structure, which has a stronger positive-Feedback regeneration during turn-on transition, will lead to a larger positive transient pole, The time when the positive transient pole occurs during CMOS latchup transition is the time when the positive-feedback regeneration starts, By this positive transient pole, the positive-feedback regenerative process of CMOS latchup can he quantitatively characterized.
MODELING THE POSITIVE-FEEDBACK REGENERATIVE PROCESS OF CMOS LATCHUP BY A POSITIVE TRANSIENT POLE METHOD .2. QUANTITATIVE-EVALUATION
(1995-06-01)
KER, MD
;
WU, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The positive-feedback regenerative process in a p-n-p-n structure during CMOS latchup transition has been modeled by a time-varying positive transient pole, The maximum peak value of the positive pole and the time required to first initiate the positive pole are adopted as two useful and meaningful parameters to quantitatively investigate the influence of device parameters on the positive-feedback regeneration of CMOS latchup. Some design guidelines can be obtained to improve latchup immunity of CMOS IC's.
TRANSIENT ANALYSIS OF SUBMICRON CMOS LATCHUP WITH A PHYSICAL CRITERION
(1994-02-01)
KER, MD
;
WU, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new physical criterion and an analytical timing model for transient latchup in a p-n-p-n structure are developed and verified. In the new physical transient latchup criterion, two new parameters called the large-signal transient current gains of the parasitic vertical and lateral BJTs in the p-n-p-n structure are defined. If their product rather than the forward beta-gain product becomes larger than unity right after triggering and remains larger than unity, the latchup occurs. With the piecewise-linearized device currents of the parasitic BJTs and the averaged junction depletion and diffusion capacitances in the p-n-p-n structure, the large-signal transient current gains are derived as functions of time and device parameters. Moreover, the dynamic behaviors and the associated timing of transient latchup can also be fully characterized. Model calculation results using the developed criterion and timing model agree very well with both SPICE simulation and experimental results. Thus the developed criterion and timing model can be applied to transient latchup analysis and prediction in CMOS ICs.