Browsing by Author "KO, J"

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A NEW DRAIN ENGINEERING STRUCTURE-SCD-LDD (SURFACE COUNTER DOPED LDD) FOR IMPROVED HOT-CARRIER RELIABILITY
(1993-09-01)
CHOU, JW
;
CHANG, CY
;
HO, LT
;
KO, J
;
HSUE, P
A new SCD-LDD (Surface Counter Doped LDD) structure is proposed. This structure introduces an additional oblique BF2 implant after nLDD implant, which counter-dopes the nLDD surface concentration near the gate edge. As a result, the lateral electric fields beneath the gate were reduced and the saturation drain current was conducted downward away from the maximum electric fields, resulting in a substantial enhancement of hot carrier reliability due to suppression of hot carrier generation and injection with this structure.
A NEW ON-CHIP ESD PROTECTION CIRCUIT WITH DUAL PARASITIC SCR STRUCTURES FOR CMOS VLSI
(1992-03-01)
WU, CY
;
KER, MD
;
LEE, CY
;
KO, J
;
電控工程研究所
A new CMOS on-chip electrostatic discharge (ESD) protection circuit which consists of dual parasitic SCR structures is proposed and investigated. Experimental results show that with a small layout area of 8800-mu-m2, the protection circuit can successfully perform negative and positive ESD protection with failure thresholds greater than +/- 1 and +/- 10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. The low ESD trigger voltages in both SCR's can be readily achieved through proper circuit design and without involving device or junction breakdown. The input capacitance of the proposed protection circuit is very low and no diffusion resistor between I/O pad and internal circuits is required, so it is suitable for high-speed applications. Moreover, this ESD protection circuit is fully process compatible with CMOS technologies.
AN ON-CHIP ESD PROTECTION CIRCUIT WITH COMPLEMENTARY SCR STRUCTURES FOR SUBMICRON CMOS ICS
(1994)
KER, MD
;
WU, CY
;
JIANG, HC
;
LEE, CY
;
KO, J
ANOMALOUS REVERSE SHORT-CHANNEL EFFECT IN P+ POLYSILICON GATED P-CHANNEL MOSFET
(1994-11-01)
CHANG, CY
;
LIN, CY
;
CHOU, JW
;
HSU, CCH
;
PAN, HT
The boron-penetration-dependent Reverse Short Channel Effect (RSCE) on the threshold voltage is observed for short channel p+ poly-gate PMOSFET's. The RSCE is found to be more significant as the boron penetration becomes more severe. The RSCE is significant in BF2 doped poly-gated MOS devices and is alleviated in buffered poly-gated MOS devices. Fluorine enhanced boron diffusion in the gate oxide during high temperature process is believed to account for the RSCE, which is also confirmed by using a two-dimensional process simulator.
CHARGE LOSS DUE TO AC PROGRAM DISTURBANCE STRESSES IN EPROMS
(1993-09-01)
LIN, JK
;
CHANG, CY
;
WANG, TH
;
HUANG, HS
;
CHEN, KL
Charge loss in interpolyoxide erasable programmable read-only memories (EPROMs) due to program disturbance by alternating current pulses applied to the drain was studied for the first time. It was found that the charge loss due to ac stress is more severe than that due to dc stress. Experimental results reveal that the more positive the floating gate potential, the more severe is the drain ac disturbance observed. The main reason for the charge loss is the displacement current which agitates the charges in the floating gate, creating a leakage path from the floating gate to the drain, in which the drain-to-floating-gate overlapping capacitance C(fd) plays an important role. The drain dc stresses of interpolyoxide/nitride/oxide (ONO) EPROMs were also measured under different bias conditions and temperatures. The data show that higher dc electric field of the floating gate to the drain results in larger V(th) shift, which can be accelerated by elevated temperature. In addition, the control gate ac stress-enhanced drain dc disturbance was also measured. We proposed that the dc drain stress is applied during the ac gate stress, which results in a heating effect. The results support the concept of dielectric ac heating.
NEW LARGE-ANGLE TILT IMPLANTED DRAIN STRUCTURE - SURFACE COUNTER-DOPED-LIGHTLY DOPED DRAIN FOR HIGH HOT-CARRIER RELIABILITY
(1994-07-01)
CHOU, JW
;
CHANG, CY
;
HUANG, C
;
HO, LT
;
KO, J
A new surface counterdoped-lightly doped drain (SCD-LDD) structure with large angle tilt (LAT) implantation is proposed in this study. This structure introduces an additional larger tilt angle and lower-energy BF2 implant after the n- implant, which counterdopes the n- surface concentration to achieve a gate/n- fully overlapped, buried and sloped n- region inside the gate edge. As a result, the lateral electric fields inside the gate edge are reduced and pushed deeper into the substrate. In addition to a reduction in substrate current, this profile also suppresses hot carrier injection by driving the current away from the surface and the maximum electric field; then it shifts the avalanche region further into the bulk Si. This consequently produces a more effective enhancement of hot carrier reliability than that of conventional LDD's and controlled large-angle-tilt implanted drains (LATID's) for submicron VLSI circuits under 5 V operation. In conclusion, this SCD-LDD provides one more degree of freedom in optimizing the n- region doping profiles as a new LATID structure.