Browsing by Author "KU, TK"

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A NEW FABRICATION TECHNOLOGY FOR FIELD-EMISSION TRIODES WITH EMITTER-GATE SEPARATION OF 0.18-MU-M
(1995-01-01)
WANG, CC
;
LEE, WF
;
KU, TK
;
CHEN, MS
;
FENG, MS
A new fabrication technology has been used for field-emission triodes with the emitter-gate separation as small as 0.18 mum to reduce the turn-on and anode voltages. The technology is based on the thermal oxidation of silicon and low-pressure chemical vapor deposition (LPCVD) of polycrystalline silicon, making the fabrication of a sub-half-micronmeter gate opening easy and reproducible. The entire process requires use of only one photolithography mask, and does not require advanced high-resolution photolithographic techniques. In this device, the oxidation process serves the three purposes of sharpening the emitters, defining the emitter-gate separation, and achieving a high-quality insulator. The finished devices have the emitter situated exactly at the center of the gate opening due to a self-alignment process. Furthermore, the LPCVD polysilicon film can form gate electrodes with a smooth edge and a small gate opening due to excellent step coverage.
SIMULATION OF THE ELECTRICAL CHARACTERISTICS OF FIELD-EMISSION TRIODES WITH VARIOUS GATE STRUCTURES
(1995-10-01)
KU, TK
;
CHEN, MS
;
WANG, CC
;
FENG, MS
;
HSIEH, IJ
A new two-dimensional numerical simulation which can accurately reproduce the empirical electrical characteristics of vertical field-emission triodes (FET's) with various gate geometries has been developed. The electrical characteristics of volcano-shaped-gate FET's were simulated for the first time and compared with those of planar-gate ones. Volcano-shaped-gate FET's exhibit significant advantages over planar-gate ones due to their superior current-voltage (I-V) properties and larger tolerance of fabrication error. A reasonable definition of emission area was obtained by applying the non-uniform current density model. For sub-micron gate aperture, the gate current is obvious only if the device structure is deeply tip-recessed. On the basis of the evaluation of the device structures including the tip cone angle, the related tip-to-gate height, the emitter shape, and the shrinkage of gate aperture, a high-aspect-ratio conical emitter with a small tip radius will be the optimum structure of FET's for low-voltage operation.