Browsing by Author "KUO, HC"

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MULTIPLE-INPUTS SYSTOLIC PRIORITY QUEUE FOR FAST SEQUENTIAL-DECODING OF CONVOLUTIONAL-CODES
(1995-10-01)
KUO, HC
;
WEI, CH
;
電控工程研究所
;
電信研究中心
;
Institute of Electrical and Control Engineering
The operating speed of a sequential decoder with stack algorithm is usually limited by the time to search the best node for further extension. This problem can be completely alleviated by using the systolic priority queue to replace the stack memory. However, the systolic priority queues developed previously are accessible only in the cases when the number of inputs processed is small. This is because the complexity of a queue grows up quickly as the volume of data flowing through it increases. Since the largest amount of data flowing through a systolic priority queue is equal to the number of inputs to this queue, the systolic priority queue is not suitable for a system with many inputs. A modified version of previously developed circuits is proposed. The number of transmission gates required in this circuit is proportional to 3N instead of N-2, where N is the number of inputs. And the total number of control signals is proportional to 3N(2) instead of N-3. But the number of comparators required is proportional to C-2(N+1), as before. This modified circuit can be used in cases where the number of inputs is small (N less than or equal to 8). A new algorithm for the multiple-inputs systolic priority queue (MISPQ) is proposed. By using this algorithm, a MISPQ may be implemented with several smaller queues, each is used to process a part of data in the MISPQ. Since the volume of data flowing through each queue is small, these queues will be simpler. However, some additional circuits should be used for the interactions between queues. A circuit for implementing this algorithm is presented and its complexity is analysed. The number of transmission gates for the MISPQ is proportional to 3N, the number of control signals is proportional to (3N(2)/2), and the number of comparators is proportional to 4C(2)(N/2+1). Thus this new architecture is feasible for large N (e.g. N greater than or equal to 8).
REDUCED COMPLEXITY SEQUENTIAL-DECODING SCHEME FOR THE MULTIPLE TRELLIS-CODED MODULATION (MTCM)
(1994)
KUO, HC
;
WEI, CH
;
電控工程研究所
;
Institute of Electrical and Control Engineering
SEQUENTIAL-DECODING OF CONVOLUTIONAL-CODES BY A COMPRESSED MULTIPLE QUEUE ALGORITHM
(1994-08-01)
KUO, HC
;
WEI, CH
;
電控工程研究所
;
電信研究中心
;
Institute of Electrical and Control Engineering
The conventional multiple stack algorithm (MSA) is an efficient approach for solving erasure problems in sequential decoding. However, the requirements of multiple stacks and large memory make its implementation difficult. Furthermore, the MSA allows only one stack to be in use at a time: the other stacks will stay idle until the process in that stack is terminated. Thus it seems difficult to implement the MSA with parallel processing technology. A two-stack scheme is proposed to achieve similar effects to the MSA. The scheme greatly reduces the loading for data transfer and I/O complexity required in the MSA, and makes parallel processing possible. An erasure-free sequential decoding algorithm for convolutional codes, the compressed multiple-queue algorithm (CMQA), is introduced, based on systolic priority queue technology, which can reorder the path metrics in a short and constant time. The decoding speed will therefore be much faster than in traditional sequential decoders using sorting methods. In the CMQA, a systolic priority queue is divided into two queues by adding control signals, thereby simplifying implementation. Computer simulations show that the CMQA outperforms the MSA in bit error rate, with about one-third the memory requirement of the MSA.