Browsing by Author "Kang, TK"

Now showing 1 - 13 of 13

A novel technology to reduce the antenna charging effects during polysilicon gate electron-cyclotron-resonance etching
(1996-07-01)
Cheng, HC
;
Kang, TK
;
Ku, TK
;
Dai, BT
;
Chen, LP
A novel technique, which uses Cl-2/O-2 mixed gas in the electron cyclotron resonance (ECR) etching system, has been proposed to remove the antenna charging effect of the MOS capacitors with 5-nm-thick oxides during polysilicon gate etching. The Cl-2/O-2 can cause the trenching effect and prevents the gate oxide from the charging damage. Furthermore, the ECR system can provide high polysilicon/oxide selectivity so that the Si substrate under gate oxide is not directly bombarded by the ions. Consequently, the E(bd) degradation of the MOS capacitors disappears as the trenching effect is apparent by using moderate Cl-2/O-2 mixed gas.
A novel two-step etching to suppress the charging damages during metal etching employing helicon wave plasma
(1998-06-01)
Cheng, HC
;
Lin, W
;
Kang, TK
;
Perng, YC
;
Dai, BT
A two-step etching has been performed to eliminate the plasma charging damages during helicon-wave plasma metal etching without selectivity loss, This technique utilized a normal etching recipe to remove the Al film and followed by an optimized etching recipe for the overetching step. By increasing the bias power and decreasing the source power, the optimum etching recipe can cause the plasma more directionally and reduce the Al charging damages. Eventually, the damage mechanism was also reported.
Antenna charging effects on the electrical characteristics of polysilicon gate during electron cyclotron resonance etching
(1996-02-01)
Kang, TK
;
Ueng, SY
;
Dai, BT
;
Chen, LP
;
Cheng, HC
The nonuniformity of the induced leakage current in metal oxide semiconductor (MOS) capacitors has been investigated in an electron cyclotron resonance (ECR) system. For plasma-etched MOS capacitors with 5-nm-thick oxides, it is found that the leakage currents induced by plasma etching increase with increasing overetching time. However, additional E(bd) (breakdown held) degradation is not obvious as overetching percentage increases from 10% to 50%. A mechanism based on the antenna charging effect has been proposed to explain the E(bd) electrical characteristics. In accordance with the mechanism, the E(bd) degradation has been significantly reduced by first etching off a narrow peripheral edge around the gate pattern.
Charging damages to gate oxides in a helicon O-2 plasma
(1997-12-01)
Lin, W
;
Kang, TK
;
Perng, YC
;
Dai, BT
;
Cheng, HC
After the exposure of metal oxide semiconductor (MOS) capacitors with antenna structures to the helicon O-2 plasma, the leakage current. charge-to-breakdown (Q(bd)) and capacitance-voltage (C-V) curves have been characterized to realize the charging damages. The results indicate that the quasi static C-V(QSCV) distortion and Q(bd) depend on the exposure time rather than the antenna ratio. The QSCV and Q(bd) Show a two stage degradation as the exposure time increases. The leakage current increases slightly for the specimens exposed to the plasma for less than 120 s, and increases considerably for the ones with the exposure time of 300 s. Based on these results, the degradation mechanism of gate oxides under the helicon O-2 plasma is established.
Charging damages to gate oxides in a helicon O-2 plasma
(1997-12-01)
Lin, W
;
Kang, TK
;
Perng, YC
;
Dai, BT
;
Cheng, HC
After the exposure of metal oxide semiconductor (MOS) capacitors with antenna structures to the helicon O-2 plasma, the leakage current. charge-to-breakdown (Q(bd)) and capacitance-voltage (C-V) curves have been characterized to realize the charging damages. The results indicate that the quasi static C-V(QSCV) distortion and Q(bd) depend on the exposure time rather than the antenna ratio. The QSCV and Q(bd) Show a two stage degradation as the exposure time increases. The leakage current increases slightly for the specimens exposed to the plasma for less than 120 s, and increases considerably for the ones with the exposure time of 300 s. Based on these results, the degradation mechanism of gate oxides under the helicon O-2 plasma is established.
Edge quantum yield in n-channel metal-oxide-semiconductor field-effect transistor
(2004-08-01)
Kang, TK
;
Su, KC
;
Chang, YJ
;
Chen, MJ
;
Yeh, SH
The quantum yield of impact ionization is performed on an n-channel metal-oxide-semiconductor field-effect transistor (n-MOSFET) by a carrier separation measurement. When the n-MOSFET is biased in accumulation, the carrier separation measurement demonstrates that the gate current mainly originates from the electrons injected into the underlying drain/source overlap regions. The measured substrate current is due to excess holes originating from the impact ionization of the injected electrons in the overlap regions. Therefore, the quantum yield in the overlap regions can be determined by the ratio of the substrate current to the gate current. It is well matched with the theoretical calculation of quantum yield. (C) 2004 American Institute of Physics.
Effects of helicon-wave-plasma etching on the charging damage of aluminum interconnects
(1998-07-01)
Lin, W
;
Kang, TK
;
Perng, YC
;
Dai, BT
;
Cheng, HC
The etching parameters of aluminum in the helicon wave plasma are characterized to elucidate the mechanism of charging damage. By increasing the ion energy and decreasing the plasma density via increase of the bias power and decrease of the source power, respectively, we can significantly reduce charging damage, On the basis of this concept, we develop a two-step etching technique to suppress the charging damage without selectivity loss. Such a high-density plasma etching technique will be very suitable for the formation of high-density, and narrow-line interconnects.
Forward gated-diode measurement of filled traps in high-field stressed thin oxides
(2000-08-01)
Chen, MJ
;
Kang, TK
;
Huang, HT
;
Liu, CH
;
Chang, YJ
The forward gated-diode monitoring technique can find its potential applications in assessing the filled traps in MOSFET thin oxides, which are subjected to high-field stressing and then followed by hot-electrons filling scheme. Our measurement of the gate voltage shift associated with the forward current peak produces a power lan relation between the filled trap density and the electron stress fluence, indeed in close agreement with that obtained by MOSFET threshold voltage shift.
Low-frequency noise in n-channel metal-oxide-semiconductor field-effect transistors undergoing soft breakdown
(2001-01-01)
Chen, MJ
;
Kang, TK
;
Lee, YH
;
Liu, CH
;
Chang, YJ
For 3.3-nm thick gate oxide n-channel metal-oxide-semiconductor field-effect transistors subject to a stress gate voltage of 5.5 V, three distinct events are encountered in the time evolution of the gate current: stress-induced leakage current (SILC), soft breakdown (SBD), and hard breakdown (HBD). The localization of SBD and HBD paths, as well as their developments with the time, is determined electrically, showing random distribution in nature. At several stress times, we interrupt the stressing to measure the drain current low-frequency noise power S-id. As expected, S-id follows up the spontaneous changes at the onset of SBD and HBD. The S-id spectra measured in fresh and SILC mode are reproduced by a literature model accounting for the carrier number and surface mobility fluctuations in the channel, and, as a result, both preexisting and newly generated trap densities are assessed. The post-SBD S-id does originate from current fluctuations in the SBD percolation paths, which can couple indirectly to drain via underlying channel in series, or directly to drain if the SBD path is formed close to drain extension. In particular, a fluctuation in S-id itself in the whole SBD duration is observed. This phenomenon is very striking since it indeed evidences the dynamic percolation origin concerning the trapping-detrapping processes in and around the SBD paths. The subsequent HBD duration remarkably features a flat S-id, indicating the set-up of a complete conductive path prevailing over the trapping-detrapping processes. (C) 2001 American Institute of Physics.
Numerical confirmation of inelastic trap-assisted tunneling (ITAT) as SILC mechanism
(2001-10-01)
Kang, TK
;
Chen, MJ
;
Liu, CH
;
Chang, YJ
;
Fan, SK
This paper presents a quite comprehensive procedure covering both the stress-induced leakage current (SILC) and oxide breakdown, achieved by balancing systematically the modeling and experimental works. The underlying model as quoted in the literature features three key parameters: the tunneling relaxation time tau, the neutral electron trap density N-t, and the trap energy level E-t. First of all, 7-nm thick oxide MOS devices with wide range oxide areas are thoroughly characterized in terms of the optically induced trap filling, the charge-to-breakdown statistics, the gate voltage developments with the time, and the SILC I-V. The former three are involved together with a percolation oxide breakdown model to build N-t explicitly as function of the stress electron fluence. Then the overall tunneling probability is calculated, with which a best fitting to SILC I-V furnishes tau of 4.0 x 10(-13) s and E-t of 3.4 eV. The extracted tau is found to match exactly that extrapolated from existing data. Such striking consistencies thereby provide evidence that inelastic trap-assisted tunneling (ITAT) is indeed the SILC mechanism. Differences and similarities of the involved physical parameters between different studies are compared as well.
Optimization of back side cleaning process to eliminate copper contamination
(2005)
Chou, WY
;
Tsui, BY
;
Kuo, CW
;
Kang, TK
;
電子工程學系及電子研究所
Copper (Cu) contamination at the wafer bevel, back side surface, and exclusion zone is identified step-by-step following a typical dual-damascene process. The shield ring of a physical vapor deposition system does not protect the exclusion zone and bevel efficiently. Also, Cu may dissolve and accumulate in the solvent used for post dielectric etch clean. Dissolved Cu atoms may then redeposit on the wafer surface. Furthermore, the rough back side surface traps Cu atoms easier than the smooth front side surface. If there is no SiO2 film on the back side surface, post chemical mechanical polish cleaning using dilute HF cannot remove Cu at the back side surface. An optimized single-wafer spin-etch process was proposed. An optimal etchant consisting of HF, HNO3, H2SO4, and H3PO4 with ratios 0.5 :3 :1 :0.5 showed excellent performance. Experiments demonstrated that a very short, 10 s, back side clean can totally remove Cu from back side surface, bevel, and 2 mm exclusion zone. A "wafer shift" procedure was also proposed to solve the pinmark issue near the edge pin due to etchant remnant. The optimized cleaning technique shows shorter process time and higher cleaning efficiency than those reported previously. (C) 2005 The Electrochemical Society.
Oxide thinning percolation statistical model for soft breakdown in ultrathin gate oxides
(2000-07-24)
Chen, MJ
;
Kang, TK
;
Liu, CH
;
Chang, YJ
;
Fu, KY
An existing cell-based percolation model with parameter correlation can find its potential applications in assessing soft-breakdown (BD) statistics as long as the oxide thinning due to the localized physical damage near the SiO2/Si interface is accounted for. The resulting model is expressed explicitly with the critical trap number per cell n(BD) and the remaining oxide thickness t(ox)(') both as parameters. Reproduction of time-to-bimodal (soft- and hard-) breakdown statistical data from 3.3-nm-thick gate-oxide samples yields n(BD) of 3 and 4 for soft and hard breakdown, respectively. The extracted t(ox)(') of 1.0 nm for soft breakdown, plus the transition layer thickness of 0.5 nm in the model, is fairly comparable with literature values from current-voltage fitting. The dimension and area of the localized physically damaged region or percolation path (cell) are quantified as well. Based on the work, the origins of soft and hard breakdown are clarified in the following: (i) soft breakdown behaves intrinsically as hard breakdown, that is, they share the same defect (neutral trap) generation process and follow Poisson random statistics; (ii) both are independent events corresponding to different t(ox)(') requirements; and (iii) hard breakdown takes place in a certain path located differently from that for the first soft breakdown. (C) 2000 American Institute of Physics. [S0003-6951(00)02130-6].
Stability investigation of single-wafer process by using a spin etcher
(2003-07-01)
Kang, TK
;
Wang, CC
;
Tsui, BY
;
Yang, WL
;
Chien, FT
Etch rate instability was found in a spin etcher. When chemical was pumped to the spin etcher, the flow rate became unstable; possibly resulting in a chemical deficiency due to low mass transport at the wafer edge. Consequently, the etch rate and etch uniformity are unstable. The detailed etch mechanism has been investigated and the mass transport deficiency can be avoided. Less than 2% of etch nonuniformity and a stable process can be achieved by achieving a stable flow rate and control of the surface reaction over the whole wafer in spin etching. (C) 2003 The Electrochemical Society.