Browsing by Author "Kang, Tsung-Kuei"

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A New Charge-Trap-Engineered Memory Device with Silicon-Oxide-Nitride-Vacuum-Silicon (SONVAS) Structure for LTPS-TFT-Based Applications
(2010)
Liao, Ta-Chuan
;
Wu, Chun-Yu
;
Chen, Sheng-Kai
;
Yu, Ming H.
;
Kang, Tsung-Kuei
For the first time, a new Silicon-Oxide-Nitride-Vacuum-Silicon (SONVAS) LTPS-TFT-based charge-trapping memory integrated on a gate-all-around field-enhanced-nanowire architecture was demonstrated. The vacuum, simply formed by an in-situ encapsulation, substituted for the traditional tunneling oxide. Due to the lowest-k and empty properties of vacuum, SONVAS features electric field enhancement in tunneling layer and immunity against the creation of interface traps and the charge trapping in the damaged tunneling oxide during P/E cycling, resulting in the much-improved P/E efficiency and reliability, respectively. Therefore, such vacuum-introduced SONVAS memory device with process simplicity is very suitable for the future system-on-panel (SOP) and 3D-stacking flash applications.
A Novel LTPS-TFT-Based Charge-Trapping Memory Device with Field-Enhanced Nanowire Structure
(2009)
Liao, Ta-Chuan
;
Chen, Sheng-Kai
;
Yu, Ming H.
;
Wu, Chun-Yu
;
Kang, Tsung-Kuei
A novel gate-all-around low-temperature poly-Si (LIPS) thin-film transistor (TFT) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory with field-enhanced nanowire (FEN) structure has been proposed to improve the program and erase (P/E) performance. Each nanowire inherently had three sharp corners fabricated simply by sidewall spacer formation to obtain high local electric fields. The field-enhanced carrier tunneling via such a structure led to faster PIE speed and wider memory window for the FEN-TFT SONOS as compared to the conventional planar (CP) counterpart. The improvement was also further verified with the simulation results. Such a high-performance FEN-TFT SONOS memory with process simplicity is very suitable for future system-on-panel (SOP) applications.
Effect of Nitrogen Plasma Treatment on Electrical Characteristics for Pd Nanocrystals in Nonvolatile Memory
(2010-08-01)
Kang, Tsung-Kuei
;
Liao, Ta-Chuan
;
Lin, Cheng-Li
;
Wu, Wen-Fa
;
電子工程學系及電子研究所
Pd nanocrystals (NCs) are successfully embedded in a TaN/SiO(2)/HfAlO/Si structure The initial memory window increases at a higher rate with increasing fabrication temperature of Pd NCs compared with the linear variation of Pd NC density, which is related to the thermally induced neutral traps in the HfAlO film around Pd NCs After manufacturing a TaN/SiO(2)/Pd NCs/HfAlO/Si/Al structure, the subsequent N(2) plasma treatment is conducted at 300 degrees C for 3 min The number of leakage current paths in the SiO(2) blocking layer adjacent to TaN is clearly reduced, but that of leakage current paths in SiO(2)/HfAlO around Pd NCs is slightly increased owing to the thermal stress The thermally induced neutral traps in the HfAlO film around the Pd NCs can be passivated by nitrogen atoms, which leads to the improvement of the final memory window for the Pd NC samples fabricated at 600-700 degrees C However, the intrinsic traps in the HfAlO film play an important role in memory characteristic and the final memory window is reduced by thermal densification for the Pd NC samples fabricated at 500 degrees C (C) 2010 The Japan Society of Applied Physics
Gate-All-Around Poly-Si TFTs With Single-Crystal-Like Nanowire Channels
(2011-09-01)
Kang, Tsung-Kuei
;
Liao, Ta-Chuan
;
Lin, Chia-Min
;
Liu, Han-Wen
;
Wang, Fang-Hsing
The gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with single-crystal-like nanowire (NW) channels (SCLNCs) are demonstrated and characterized. Via the nanoscale nitride spacer, the Si NW can be easily transformed within one crystalline grain of the two-shot sequential-lateral-solidification poly-Si film. As compared with the planar ones, the GAA-SCLNC TFTs showed more excellent characteristics. The results clearly show that the variations of device characteristics can be reduced by increasing the numbers of NWs in the channels and an average mobility above 410 cm(2)/V . s with a low standard deviation can be achieved for the GAA-SCLNC TFTs with 20-NW channels.
Gate-all-around polycrystalline-silicon thin-film transistors with self-aligned grain-growth nanowire channels
(2012-02-27)
Liao, Ta-Chuan
;
Kang, Tsung-Kuei
;
Lin, Chia-Min
;
Wu, Chun-Yu
;
Cheng, Huang-Chung
In this letter, gate-all-around (GAA) polycrystalline silicon thin-film transistors (TFTs) with self-aligned grain-growth channels were fabricated using excimer laser crystallization (ELC) on a recessed-nanowire (RN) structure. Via the RN structure constructed by a simple sidewall-spacer formation, location-controlled nucleation and volume-confined lateral grain growth within the RN body during ELC process have been demonstrated with only one perpendicular grain boundary in each nanowire channel. Because of the high-crystallinity channel together with GAA operation mode, the proposed GAA-RN TFTs show good device integrity of lower threshold voltage, steeper subthreshold slope, and higher field-effect mobility as compared with the conventional planar counterparts. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.3691184]
Improved characteristics for Pd nanocrystal memory with stacked HfAlO-SiO(2) tunnel layer
(2011-07-01)
Kang, Tsung-Kuei
;
Liu, Han-Wen
;
Wang, Fang-Hsing
;
Lin, Cheng-Li
;
Liao, Ta-Chuan
Stacked HfAlO-SiO(2) tunnel layers are designed for Pd nanocrystal nonvolatile memories. For the sample with 1.5 nm-HfAlO/3.5 nm-SiO(2) tunnel layer, a smaller initial memory window is obtained compared to the sample with 3.5 nm-HfAlO/1.5 nm-SiO(2) tunnel layer. Owing to the thermally induced traps in HfAlO-SiO(2) films are located at a farther distance from the Si substrate and more effective blocking of charge leakage by asymmetric tunnel barrier, a larger final memory window and better retention characteristic can be obtained for Al/blocking oxide SiO(2)/Pd NC5/1.5 nm-HfAlO/3.5 nm-SiO(2)/Si structure. A N(2) plasma treatment can further improve the memory characteristics. Better memory characteristics can be obtained for Pd-nanocrystal-based nonvolatile memory with an adequate thickness ratio of HfAlO to SiO(2). (C) 2011 Elsevier Ltd. All rights reserved.
Improved characteristics for Pd nanocrystal memory with stacked HfAlO-SiO2 tunnel layer
(2011-07-01)
Kang, Tsung-Kuei
;
Liu, Han-Wen
;
Wang, Fang-Hsing
;
Lin, Cheng-Li
;
Liao, Ta-Chuan
Stacked HfAlO-SiO2 tunnel layers are designed for Pd nanocrystal nonvolatile memories. For the sample with 1.5 nm-HfAlO/3.5 nm-SiO2 tunnel layer, a smaller initial memory window is obtained compared to the sample with 3.5 nm-HfAlO/1.5 nm-SiO2 tunnel layer. Owing to the thermally induced traps in HfAlO-SiO2 films are located at a farther distance from the Si substrate and more effective blocking of charge leakage by asymmetric tunnel barrier, a larger final memory window and better retention characteristic can be obtained for Al/blocking oxide SiO2/Pd NC5/1.5 nm-HfAlO/3.5 nm-SiO2/Si structure. A N-2 plasma treatment can further improve the memory characteristics. Better memory characteristics can be obtained for Pd-nanocrystal-based nonvolatile memory with an adequate thickness ratio of HfAlO to SiO2. (C) 2011 Elsevier Ltd. All rights reserved.
Novel Omega-Shaped-Gated TFT SONOS Memory
(2009)
Liao, Ta-Chuan
;
Chen, Sheng-Kai
;
Kang, Tsung-Kuei
;
Hsu, Pang-Yu
;
Lin, Chia-Min
A novel omega-shaped-gated (Omega-Gate) polycrystalline-silicon thin-film transistor (TFT) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory with field-enhanced nanowire (FEN) structure has been proposed to improve the program and erase (P/E) performance. Each nanowire inherently had twin sharp corners fabricated simply by sidewall spacer formation to obtain high local electric fields. The field-enhanced carrier tunneling via such a structure led to faster P/E speed and wider memory window for the Omega-Gate SONOS as compared to the conventional planar (CP) counterpart. Such an Omega-Gate-TFT SONOS memory using a simple process is very suitable for future system-on-panel applications.