Browsing by Author "Kang, Yu-Chi"

Now showing 1 - 2 of 2

Reduction of Equivalent Series Inductor Effect in Delay-Ripple Reshaped Constant On-Time Control for Buck Converter with Multi-layer Ceramic Capacitors
(2012)
Chen, Wei-Chung
;
Kang, Yu-Chi
;
Lin, Chia-Ching
;
Chen, Ke-Horng
;
Wang, Shih-Ming
The time constant, which is the product of the output capacitor and its equivalent series resistance (ESR), limits the stability of conventional constant on-time control buck converter. To meet the expected requirements, SP-CAP is mostly used as output capacitor although it deteriorates the performance of converter. On the other hand, the multi-layer ceramic capacitors (MLCC) features low cost and small equivalent series resistance (ESR) and is widely used in commercial power management ICs. However, the stability often suffers from the sub-harmonic problem due to small time constant. This paper proposes a differential-zero compensator with the noise margin enhancement (DZC-NME) technique in constant on-time control buck DC-DC converter with ceramic output capacitor. The proposed DZC-NME technique not only eliminates the limit of large time constant but also tolerates the existence of equivalent series inductor (ESL) effect. Simulation result demonstrates the function and shows smaller output ripple of 10mV and high efficiency of 91 % with ESR which smaller than 1m Omega.
Variable Sampling Slope (VSS) and No-Deadtime Ramp Generator (NDRG) Techniques for Closed-Loop Interleaving Power Factor Correction (PFC) Design with Suppression of Current Mismatch
(2012)
Chen, Chun-Yen
;
Peng, Ruei Hong
;
Tsai, Jen-Chieh
;
Kang, Yu-Chi
;
Ni, Chia-Lung
the proposed interleaving power factor correction (PFC) can effectively reduce the size of the AC-DC converter for portable electronics. Fully integrated variable sampling slope (VSS) technique can provide precise phase regulation under variable line voltage. Besides, the no-deadtime ramp generator (NDRG) records the previous status to modify the sequent on-time value to achieve current sharing for suppressing the total harmonic distortion (THD) and restraining the input current ripple, EMI filter, and the size of input inductor. Therefore, more power can be provided by the proposed interleaving PFC than that of single-phase PFC. Simultaneously, the drawback of the peak current twice than the average current in the Boundary control mode (BCM) can be greatly reduced. The test circuit fabricated in the TSMC 0.5 mu m 800V UHV process shows the highly integrated interleaving PFC can deliver high power of 180W with improved phase regulation precision.