Browsing by Author "Kao, HS"

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A 1.8GHz CMOS quadrature voltage-controlled oscillator (VCO) using the constant-current LC ring oscillator structure
(1998)
Wu, CY
;
Kao, HS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new fully integrated CMOS quadrature voltage-controlled oscillator (VCO) realized in a standard 0.5 mu m double poly double metal (DPDM) CMOS technology is proposed, that combines a fully differential two-stage ring oscillator with LC tanks and negative resistance to provide both inphase and quadrature output signals. The phase noise is low due to the use of the resonator-type oscillator. The simulation results show that with an on-chip varactor tuned resonator and a control voltage of 0-3 V, the tuning range of the VCO is 160MHz from 1.67GHz to 1.83GHz. Under 1% mismatch of the inductor or capacitor, the phase error of VCO outputs are less than 1 degrees from perfect quadrature and the amplitude ratio are less than 1.0007. The power dissipation is 35mW for 3V power supply. The area is 1.3 x 0.9 mm(2), dominated by the two integrated spiral inductors.
A 2-V low-power CMOS direct-conversion quadrature modulator with integrated quadrature voltage-controlled oscillator and RF amplifier for GHz RF transmitter applications
(2002-02-01)
Wu, CY
;
Kao, HS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A compact low-voltage low-power CMOS direct-conversion quadrature modulator with integrated quadrature voltage-controlled oscillator (VCO) and radio frequency (RF) amplifier for wireless transmitter applications is proposed and analyzed. By applying both baseband input signals with quadrature phases and quadrature local oscillator (LO) signals to a set of combiners, the quadrature modulation functions can be implemented. The low-power operation is enabled by the current reuse technique used among quadrature modulator, quadrature VCO, and RF amplifier. Because only two transistors and one resistor are cascoded in the critical path of the proposed quadrature modulator between power supply and ground, the supply voltage can be as low as 1.5 V. The proposed circuit structure is used to design a quadrature modulator chip for 1.9-GHz digital enhanced cordless telecommunications (DECT) transmitter applications. The experimental chip is fabricated by using 0.35-mum n-well double-poly-triple-metal (DPTM) CMOS technology. The power dissipation is only 18 mW under 2-V power supply voltage. The on-chip quadrature VCO can provide highly accurate quadrature signals without any phase tuning or trimming. The frequency tuning range of the quadrature VCO is 280 MHz from 1.89 to 2.17 GHz at 2-V supply voltage. Due to small mismatch among quadrature signal paths, the measured image ratio is below -42 dBc under 2-V supply voltage when the desired upper side-band (USB) is set at 2 GHz and -51 dBc under 3-V supply voltage when the desired USB at 1.94 GHz. At 2-V supply voltage, the measured LO leakage is -48 dBc. Moreover, the measured second-order intermodulation and third-order intermodulation are less than -46 dBc.
A compact CMOS 2V low-power direct-conversion quadrature modulator merged with quadrature voltage-controlled oscillator and RF amplifier for 1.9GHz RF transmitter applications
(2000)
Kao, HS
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A compact 2V CMOS low-power direct-conversion quadrature modulator merged with quadrature voltage-controlled oscillator (VCO) and RF amplifier for 1.9GHz RF transmitter applications is described. The circuit is implemented by using 0.35 mu m DPTM CMOS technology and dissipates only 19mW under 2V power supply voltage. The low power operation is enabled by the current reuse technique used among quadrature modulator, quadrature VCO, and RF amplifier. Due to small signal path mismatch, the unwanted lower sideband is below -50dB when the 0dB normalized desired upper sideband is set at 1.97GHz. Moreover, the LO feedthrough, second-order intermodulation, and third-order intermodulation are less than -50dB. The tuning range of the quadrature VCO is 270MHz from 1.95GHz to 2.22GHz.
An improved low-power CM OS direct-conversion transmitter for GHZ wireless communication applications
(2002)
Kao, HS
;
Wu, CY
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電機學院
;
College of Electrical and Computer Engineering
The proposed transmitter chip is fabricated in a standard 0.25um single-poly-five-metal CMOS process with low resistance substrate. It consists of a quadrature modulator, a quadrature VCO, and a power amplifier. This transmitter IC consumes only 45 mA from a 2.5V power supply voltage. With highly linear quadrature modulator and low phase-error quadrature VCO structure, the measured LO leakage, image rejection, second-order inter-modulation and third-order inter-modulation of the modulated signal at the output of transmitter achieve -59dBc, -57dBc, -60dBc, and -56dBc, respectively. The three-stage power amplifier is also integrated to provide a 9.8dBm output power with 15% efficiency for short-range wireless communication applications.
ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness
(2002-01-01)
Ker, MD
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Lo, WY
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Lee, CM
;
Chen, CP
;
Kao, HS
This paper presents a state-of-art ESD protection design for RF circuit with a human-body-model (HBAP ESD robustness of 8kV. By including a turn-on efficient power-rails clamp circuit into the RF circuit, the ESD clamp devices of the RF input pin are operated in the forward-biased conduction, rather than the traditional junction breakdown condition Therefore, the dimension of ESD devices for the RF input pin can be further downsized to reduce the input capacitance loading for the RF signal This design has been successfully applied in a 900-MHz RF receiver and fabricated in 0.25-mum CMOS process with a thick top metal layer. The experimental results have confirmed that its ESD robustness is as high as >8kV under the HBM ESD test.
ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness
(2002)
Ker, MD
;
Lo, WY
;
Lee, CM
;
Chen, CP
;
Kao, HS
This paper presents a state-of-art ESD protection design for RF circuit with a human-body-model (HBM) ESD robustness of ME By including a turn-on efficient power-rails clamp circuit into the RF circuit, the ESD clamp devices of the RF input pin are operated in the forward-biased conduction, rather than the traditional junction breakdown condition. Therefore, the dimension of ESD devices for the RF input pin can be further downsized to reduce the input capacitance loading for the RF signal. This design has been successfully applied in a 900-MHz RF receiver and fabricated in 0.25-mum CMOS process with a thick top metal layer. The experimental results have confirmed that its ESD robustness is as high as >8kV under the HBM ESD test.
Low-power fully integrated and tunable CMOS RF wireless receiver for ISM band consumer applications
(2005-09-01)
Li, SC
;
Kao, HS
;
Chen, CP
;
Su, CC
;
交大名義發表
A 0.25-mu m single-chip CMOS single-conversion tunable low intermediate frequency (IF) receiver operated in the 902-928-MHz industrial, scientific, and medical band is proposed. A new 10.7-MHz IF section that contains a limiting amplifier and a frequency modulated/frequency-shift-key demodulator is designed. The frequency to voltage conversion gain of the demodulator is 15 mV/kHz and the dynamic range of the limiting amplifier is around 80 dB. The sensitivity of the IF section including the demodulator and limiting amplifier is -72 dBm. With on-chip tunable components in the low-power low-noise amplifier (LNA) and LC-tank voltage-controlled oscillator circuit, the receiver measures an RF gain of 15 dB at 915 MHz, a sensitivity of -80 dBm at 0.1% bit-error rate, an input referred third-order intercept point of -9 dBm, and a noise figure of 5 dB with a current consumption of 33 mA and a 2450 mu m x 2450 mu m chip area.