Browsing by Author "Kao, Ming-Hsuan"

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A look into the origin of shunt leakage current of Cu(In,Ga)Se-2 solar cells via experimental and simulation methods
(2013-10-01)
Liao, Yu-Kuang
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Kuo, Shou-Yi
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Hsieh, Ming-Yang
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Lai, Fang-I
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Kao, Ming-Hsuan
This study investigates how to apply space-charge-limited (SCL) current to describe shunt leakage current in a CIGS solar cell. Possible factors inducing SCL current have been observed through conductive atomic force microscopy (C-AFM), which supports the SCL current theory, describing the shunt current of a CIGS solar cell. In simulations derived from experimental data, deviation of dark IV curves is due to flaws in the real device. These flaws are absent in simulation, but investigation verifies the characteristics of SCL current component's experimental IV curves within shunt leakage current. A device with a metal/CIGS/metal structure could simulate SCL current and confirm its characteristics. Such a simulated structure, representing flaws inserted into a CIGS solar cell, generates the same dark-current behavior revealed in experimental dark IV curves. This study investigates the response of dark current to varying sizes of the flaw within the CIGS solar cell. (C) 2013 Elsevier B.V. All rights reserved.
A sandwiched buffer layer enabling pulsed ultraviolet- and visible-laser annealings for direct fabricating poly-Si field-effect transistors on the polyimide
(2017-07-10)
Kao, Ming-Hsuan
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Huang, Wen-Hsien
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Shieh, Jia-Min
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Shen, Chang-Hong
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Lee, Pei-Kang
A sandwiched buffer layer of SiO2/Al/SiO2 enables ultraviolet-laser crystallization and visible-laser activation for direct fabrication of a poly-Si flexible field-effect-transistor (fFET) on polyimides. The buffer layer can produce heat accumulation and laser reflection from the Al/SiO2 interface to facilitate grain growth and contact resistance reduction of poly-Si without damaging the polyimide substrate. The feature size of poly-Si fFET has shrunk to 400nm via laser annealing, with the on/off current-ratio exceeding 5 x 10(6) and a subthreshold swing of 190 mV/dec. Moreover, the transfer characteristics of fFET by tension stress can be maintained until the bending radius reaches over 15 mm. Published by AIP Publishing.
a-SiGeC Thin Film Photovoltaic Enabled Self-Power Monolithic 3D IC Under Indoor Illumination
(2016)
Kao, Ming-Hsuan
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Yang, Chih-Chao
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Wu, Tsung-Ta
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Hsieh, Tung-Ying
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Huang, Wen-Hsieh
Low temperature a-SiGeC thin film photovoltaic (TFPV) ambient light-energy harvesters monolithically integrated with high performance 3D sequentially stackable device were demonstrated in this article. The 3D stackable device with threshold voltage engineering and driving current boosting technologies enable excellent current controllability to achieve low I-off and high I-on operation condition for integrated circuit design. The monolithically stacking of Si thin-film energy harvester, which provide output power (21.93uW/cm(2)) under 450 lux indoor illumination, envisions self-power and low cost 3D(+)IC for internet of things.
CO2 laser annealing of low-hole-concentration polycrystalline germanium for the fabrication of enhancement-mode nMOSFET
(2018-10-01)
Kasirajan, Han Anand
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Huang, Wen-Hsien
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Kao, Ming-Hsuan
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Wang, Hsing-Hsiang
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Shieh, Jia-Min
A p-type polycrystalline Ge (poly-Ge) film processed by UV and CO2 laser annealing reduces the hole concentration from 6 x 10(18) to 2 x 10(16) cm(-3), accompanied by poly-grain growth. The decrease in hole concentration arises from the defect annealing using a CO2 laser, as demonstrated by the changes in the work function, that is, the valence-band maximum (VBM). The laser processes reduce the thermal budget for the fabrication of an enhancement-mode poly-Ge nMOSFET, which has a l(on)/l(off) ratio of 5 x 10(3), a Vth of 2V, and a subthreshold swing of 250 mV/dec., and will be potential fabrication methods for monolithic 3D integrated circuits in the future. (C) 2018 The Japan Society of Applied Physics
Down Shifted Converssion for Enhanceed HIT SSolar Cell Efficiency
(2017-01-01)
Lin, Albert S.
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Parashar, Parag
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Huang, Wei-Ming
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Huang, Yi-Wen
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Jian, Ding-Rung
In this work, HIT solar cell is incorporated with the luminescent down-shifting (LDS) mechanism for the incident solar spectrum. The heterojunction with intrinsic thin-layer(HIT) solar cell is highly efficient, low temperature (200 C), low cost, and highly symmetrical device. Nevertheless, the carrier collection efficiency is low for the short wavelength solar photons due to the surface recombination. Here, a thin phosphor layer is spray coated on the top of HIT solar cells for the luminescent down-shifting of high energy photons and thus enhanced external quantum efficiency (EQE) for the device for lambda=300nm-450nm is observed.
Enabling n-type polycrystalline Ge junctionless FinFET of low thermal budget by in situ doping of channel and visible pulsed laser annealing
(2017-02)
Huang, Wen-Hsien
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Shieh, Jia-Min
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Kao, Ming-Hsuan
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Shen, Chang-Hong
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Huang, Tzu-En
A low-thermal-budget n-type polycrystalline Ge (poly-Ge) channel that was prepared by plasma in-situ-doped nanocrystalline Ge (nc-Ge) and visible pulsed laser annealing exhibits a high electrically active concentration of 2 x 10(19) cm(-3) and a narrow Raman FWHM of 3.9 cm(-1). Furthermore, the fabricated n-type poly-Ge junctionless FinFET (JL-FinFET) shows an I-on/I-off ratio of 6 x 10(4), V-th of % -0.3 V, and a subthreshold swing of 237mV/dec at V-d of 1V and DIBL of 101mV/V. The poly-Ge JL-FinFET with a high-aspect-ratio fin channel is less sensitive to V-th roll-off and subthreshold-swing degradation as the gate length is scaled down to 50 nm. This low-thermal-budget JL-FinFET can be integrated into three-dimensional sequential-layer integration and flexible electronics. (C) 2017 The Japan Society of Applied Physics
Heterogeneously integrated sub-40nm low-power epi-like Ge/Si monolithic 3D-IC with stacked SiGeC ambient light harvester
(2014)
Shen, Chang-Hong
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Shieh, Jia-Min
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Huang, Wen-Hsien
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Wu, Tsung-Ta
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Chen, Chien-Fu
For the first time, we report heterogeneously integrated sub-40nm epi-like Ge/Si monolithic 3D-IC with low-power logic/NVM circuits and efficient photovoltaic energy harvester. Threshold voltage engineering and driving current boosting technologies enable stackable Ge/Si UTB (< 15nm) MOSFETs, CMOS inverter and SRAM (SNM=270mV@0.7V) achieve low operation voltage. Stackable 1-T NVM with high speed (100ns) and low driving-voltage operation provide power-off storage while SRAM serve as power-on working memory. 100% aperture ratio SiGeC ambient light energy harvester with maximum output power of 7mW/cm(2) layered on the monolithic 3D-IC chip envisions a self-powered monolithic 3D-IC technology for advanced low-power wire-less sensor networks, wearable devices, and devices for Internet of Things.
High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits
(2017-05-02)
Wu, Tsung-Ta
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Huang, Wen-Hsien
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Yang, Chih-Chao
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Chen, Hung-Chun
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Hsieh, Tung-Ying
Development of manufacture trend for TFTs technologies has focused on improving electrical properties of films with the cost reduction to achieve commercialization. To achieve this goal, high-performance sub-50 nm TFTs-based MOSFETs with ON-current (I-on)/subthreshold swing (S.S.) of 181 mu A/mu m/107 mV/dec and 188 mu A/mu m/98 mV/dec for NMOSFETs and PMOSFETs in a monolithic 3D circuit were demonstrated by a low power with low thermal budget process. In addition, a stackable static random access memory (SRAM) integrated with TFTs-based MOSFET with static noise margins (SNM) equals to 390 mV at V-DD = 1.0 V was demonstrated. Overall processes include a low thermal budget via ultra-flat and ultra-thin poly-Si channels by solid state laser crystallization process, chemical-mechanical polishing (CMP) planarization, plasma-enhanced atomic layer deposition (ALD) gate stacking layers and infrared laser activation with a low thermal budget. Detailed material and electrical properties were investigated. The advanced 3D architecture with closely spaced inter-layer dielectrics (ILD) enables high-performance stackable MOSFETs and SRAM for power-saving IoT/mobile products at a low cost or flexible substrate.
HIT Solar Cell Performance Enhancement with Luminescent Down Shifting Phenomenon
(2018-01-01)
Lin, Albert
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Huang, Chien-Yao
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Parashar, Parag
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Chou, Hao-Ming
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Lin, Yi-Shiuan
Luminescent down-shifting (LDS) phenomenon has been employed to enhance the HIT solar cell efficiency. The efficiency and J(SC) are increased by 2.3% and 11.5% respectively. External quantum efficiency (EQE) data supports our claim.
Logic/Memory Hybrid 3D Sequentially Integrated Circuit Using Low Thermal Budget Laser Process
(2015)
Yang, Chih-Chao
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Hsieh, Tung-Ying
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Huang, Wen-Hsien
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Wu, Tsung-Ta
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Wang, Hsing-Hsiang
High performance 3D sequentially stackable nanowire FETs and non-volatile memories (NVMs) with threshold voltage engineering and driving current boosting technologies were demonstrated by using low thermal budget nanosecond laser crystallization and laser activation technologies. The local heating laser process without damaging the underlying device/circuit realizes the across -layer and in -layer integration of high-speed 3ps logic circuits and 1-T 100ns plasma-MONOS NVMs as well as low driving-voltage 6T SRAMs with static noise margin (SNM) of 280 mV. Such logic/memory hybrid 3D sequentially integrated circuit provides power efficient computing and storage. Moreover, the monolithically stacking of Si thin-film energy harvester envisions lower power and low cost 3D(+)IC for internet of things.
Low Temperature a-SiGe:H Near-IR Sensor and Photovoltaic Devices for Flexible Multi-functional Panel
(2013-01-01)
Kao, Ming-Hsuan
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Shieh, Jia-Min
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Shen, Chang-Hong
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Yu, Peichen
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Kuo, Hao-Chung
High Near-IR response photo-diode (0.1A/W@800nm) and high efficiency a-Si/a-SiGe tandem solar cell (8.38%) were demonstrated using high-density plasma-fabricated a-SiGe:H deposition technology with Si2H6 and GeH4 precursor. The low temperature (140 degrees C) a-SiGe: H films with low defect density (2.3x10(16)cm(-3)) are suitable for the applications of flexible solar self-powered multi-functional panel and 3D stacked monolithic devices.
Low-Temperature Growth of Hydrogenated Amorphous Silicon Carbide Solar Cell by Inductively Coupled Plasma Deposition Toward High Conversion Efficiency in Indoor Lighting
(2017-10-05)
Kao, Ming-Hsuan
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Shen, Chang-Hong
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Yu, Pei-chen
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Huang, Wen-Hsien
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Chueh, Yu-Lun
A p-a-SiC:H window layer was used in amorphous Si thin film solar cells to boost the conversion efficiency in an indoor lighting of 500 lx. The p-a-SiC: H window layer/p-a-Si:H buffer layer scheme moderates the abrupt band bending across the p/i interface for the enhancement of V-OC, J(SC) and FF in the solar spectra of short wavelengths. The optimized thickness of i-a-Si:H absorber layer is 400 nm to achieve the conversion efficiency of similar to 9.58% in an AM1.5 G solar spectrum. However, the optimized thickness of the absorber layer can be changed from 400 to 600 nm in the indoor lighting of 500 lx, exhibiting the maximum output power of 25.56 mu W/cm(2). Furthermore, various durability tests with excellent performance were investigated, which are significantly beneficial to harvest the indoor lights for applications in the self-powered internet of thing (IoT).
Modeling and Optimization of Sub-Wavelength Grating Nanostructures on Cu(In,Ga)Se-2 Solar Cell
(2012-10-01)
Kuo, Shou-Yi
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Hsieh, Ming-Yang
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Lai, Fang-I
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Liao, Yu-Kuang
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Kao, Ming-Hsuan
In this study, an optical simulation of Cu(In,Ga)Se-2 (CIGS) solar cells by the rigorous coupled-wave analysis (RCWA) method is carried out to investigate the effects of surface morphology on the light absorption and power conversion efficiencies. Various sub-wavelength grating (SWG) nanostructures of periodic ZnO:Al (AZO) on CIGS solar cells were discussed in detail. SWG nanostructures were used as efficient antireflection layers. From the simulation results, AZO structures with nipple arrays effectively suppress the Fresnel reflection compared with nanorod- and cone-shaped AZO structures. The optimized reflectance decreased from 8.44 to 3.02% and the efficiency increased from 14.92 to 16.11% accordingly. The remarkable enhancement in light harvesting is attributed to the gradient refractive index profile between the AZO nanostructures and air. (C) 2012 The Japan Society of Applied Physics
Monolithic 3D SRAM-CIM Macro Fabricated with BEOL Gate-All-Around MOSFETs
(2019-01-01)
Hsueh, Fu-Kuo
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Lee, Chun-Ying
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Xue, Cheng-Xin
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Shen, Chang-Hong
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Shieh, Jia-Min
For the first time, below 400 degrees C-fabricated gate-all-around (GAA) transistor fabrication process was demonstrated with monolithic computing-in-memory (CIM) circuit. Key enablers are plasma-assisted atomic layer etching (PA-ALE), plasma immersion ion implantation (PIII) and far-infrared laser activation (FIR-LA). The 3D stackable single-grained Si GAA MOSFETs thus fabricated exhibit record-high I-on/I-off ratio (similar to 10(8)) with low I-off (pFETs<10(-2) nA/mu m). Moreover, the stackability of the GAA MOSFETs and the differential output of dual-mode 10T SRAM readout enable 2x throughput in the CIM circuitry.
Multi-functional stacked light-trapping structure for stabilizing and boosting solar-electricity efficiency of hydrogenated amorphous silicon solar cells
(2013-08-12)
Huang, Wen-Hsien
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Shieh, Jia-Min
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Pan, Fu-Ming
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Shen, Chang-Hong
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Huang, Jung Y.
A sandwiched light-trapping electrode structure, which consists of a capping aluminum-doped ZnO (AZO) layer, dispersed plasmonic Au-nanoparticles (Au-NPs), and a micro-structured transparent conductive substrate, is employed to stabilize and boost the conversion-efficiency of hydrogenated amorphous silicon (a-Si:H) solar cells. The conformal AZO ultrathin layer (5 nm) smoothened the Au-NP-dispersed electrode surface, thereby reducing defects across the AZO/a-Si:H interface and resulting in a high resistance to photo-degradation in the ultraviolet-blue photoresponse band. With the plasmonic light-trapping structure, the cell has a high conversion-efficiency of 10.1% and the photo-degradation is as small as 7%. (C) 2013 AIP Publishing LLC.
Non-reciprocal meta-surfaces for nanophtonic light trapping: optical isolators versus solar cells
(2015)
Fu, Sze Ming
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Zhong, Yan Kai
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Yan, Sheng Lun
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Ju, Nyan Ping
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Chen, Po Yu
Nano-photonic concept has been shown to be very effective for boosting solar cell conversion efficiency. In this work, the novel concepts of non-reciprocality and chiral meta-surface are demonstrated to be very useful for photovoltaics. The asymmetric chiral patterns are designed and optimized using genetic algorithm. The enhanced optical absorption is observed and it is attributed to the non-reciprocal nature of the solar cell front meta-surface. The asymmetric solar cell front surface enhances the anti-reflection and, at the same time, forbids the photon escape once it enters the devices. This concept is very similar to optical isolators where one-way transmission is intentionally designed for enhanced optical diode effect. Preliminary experimental results are supplied to confirm the superiority of asymmetric chiral design. The ongoing experimental effort is adjusting the PECVD deposition conditions to boost the efficiency on patterned substrates.
Performance Characterization of Dye-Sensitized Photovoltaics under Indoor Lighting
(2017-04-20)
Chen, Chia-Yuan
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Jian, Zih-Hong
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Huang, Shih-Han
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Lee, Kun-Mu
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Kao, Ming-Hsuan
Indoor utilization of emerging photovoltaics is promising; however, efficiency characterization under room lighting is challenging. We report the first round-robin interlaboratory study of performance measurement for dye-sensitized photovoltaics (cells and mini-modules) and one silicon solar cell under a fluorescent dim light. Among 15 research groups, the relative deviation in power conversion efficiency (PCE) of the samples reaches an unprecedented 152%. On the basis of the comprehensive results, the gap between photometry and radiometry measurements and the response of devices to the dim illumination are identified as critical obstacles to the correct PCE. Therefore, we use an illuminometer as a prime standard with a spectroradiometer to quantify the intensity of indoor lighting and adopt the reverse-biased current voltage (I-V) characteristics as an indicator to qualify the I-V sampling time for dye-sensitized photovoltaics. The recommendations can brighten the prospects of emerging photovoltaics for indoor applications.
Photonic Density of State (PDOS) Enhancement by Brillouin Zone Engineering
(2015)
Fu, Sze Ming
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Zhong, Yan Kai
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Yan, Sheng Lun
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Ju, Nyan Ping
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Chen, Po Yu
The material absorption can be enhanced by increased photonic density of state(PDOS). Here we demonstrate that through the design in the Brillouin zone of nanophotonic light trapping structures, the PDOS can be effectively increased. The theoretical work using rigorously coupled wave calculation shows the increased spectral absorption and the optimal quasi-guided mode excitations in terms of their quality factors and the number of excited modes. The experimental work is currently ongoing and the preliminary result confirms enhanced short circuit current if the PDOS is properly adjusted. Unlike random structures, the proposed Brillouin zone engineered structures are more feasible from modeling and device process viewpoints.
The External Light Trapping for Perovskite Solar Cells Using Nanoimprinted Polymer Metamaterial Patterns
(2016-01-01)
Lin, Albert
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Fu, Sze Ming
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Chen, Bo-Ruei
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Yan, Sheng-Lun
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Zhong, Yan Kai
In this work, we develop the process flow for nano-imprinted metamaterial patterns for perovskite solar cell light trapping. Nanoimprint can be scaled for large-area photovoltaics at low cost, compared to conventional lithography techniques. While conventional grating is normally underneath the solar cell active layers, the degraded electrical characteristic can be a problem. On the other hand, the external light trapping separates the electrical and optical designs and, therefore, it is more promising for complex photonic management without sacrificing the diode characteristics. We demonstrate the concept by perovskite solar cells with metamaterial patterns. Imprinting a deeper metamaterial pattern is suggested to enhance the far field effect for further efficiency improvement.
The External Light Trapping Using Down-Conversion Polymer and Diffuse Trench Reflectors
(2016-01-01)
Lin, Albert
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Han, Hau-Vei
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Huang, Chien-Yao
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Chen, Bo-Ruei
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Fu, Sze Ming
External light trapping has been proposed as an alternative to internal light trapping. The advantage is that the electrical and optical characteristics can be designed separately. This enhances the degree of improvement that nano-photonics can contribute to the solar cell efficiency and J(SC). In this work, we use diffuse trench reflectors with down-conversion polymer to demonstrate the concepts of a low-cost, widely applicable scheme for the external light trap. A >50% enhancement of the J(SC) can be observed with proper designs and configurations. The proposed external light trap can be applied to nearly all thin-film solar cell technologies since the external optical components do not affect the electrical diode characteristic of the solar cells. The efficient external light trap is attributed to the high reflectance of the disuse mirror and its wide-angle diffractions, optical confinement due to the trench reflector, and the additional short-wavelength spectral enhancement by the down-conversion mechanism.