Browsing by Author "Kao, YC"

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Impact of thermal stability on the characteristics of complementary metal oxide semiconductor transistors with TiN metal gate
(2002-02-01)
Wang, MF
;
Huang, TY
;
Kao, YC
;
Lin, HC
;
Chang, CY
The effects of rapid thermal annealing (RTA) performed after source/drain (S/D) implantation on the characteristics of complementary metal-oxide-semiconductor (CMOS) transistors with a TiN metal gate were investigated thoroughly. It was shown that n-channel devices require a higher thermal budget in order to reduce junction leakage, compared to p-channel devices. It was also found that the flat-band voltage and oxide thickness are both affected by the annealing temperature, particularly for p-channel devices. In n-channel devices, the gate leakage current level is highly dependent on channel length and RTA temperatures. Further analysis indicated that the agglomeration phenomenon during the high-temperature RTA step occurs more easily as the metal gate length becomes narrower. When this happens, gate oxide integrity is degraded, resulting in an increased gate leakage of n-channel transistors.
New triple self-aligned (SA3) split-gate flash cell with T-shaped source coupling
(2005-10-01)
Sung, HC
;
Lei, TF
;
Huang, CM
;
Kao, YC
;
Lin, YT
A new triple self-aligned (SA3) split-gate flash cell with a T-shaped source coupling approach is described in this paper. This novel structure can significantly enhance coupling capacitance between the Source and floating gate without increasing cell size. The enhancement can be simply modulated by an oxide-etching step. This new structure can be applied to program voltage reduction and cell size scaling. For program voltage reduction, the maximum program voltage of the new cell can be reduced from 7.4 to 6AV, which is characterized by a newly developed methodology for program vs disturb window characterization. For cell size scaling, comparable sort-1 and sort-2 yields are demonstrated using the new cell with a shorter floating length and a shallower source junction. To understand the relationship between source coupling ratio (SCR) and the program/erase mechanism, an insightful discussion on the program and erase mechanisms for our split-gate flash cell is also shown in this paper.
Novel program versus disturb window characterization for split-gate flash cell
(2005-03-01)
Sung, HC
;
Lei, TF
;
Hsu, TH
;
Kao, YC
;
Lin, YT
In this letter, a new methodology for program versus disturb window characterization on split gate Flash cell is presented for the first time. The window can be graphically illustrated in V-wI (word-line)-V-ss (source) domain under a given program current. This method can help us understand quantitatively how the window shifts versus bias conditions and find the optimal program condition. The condition obtained by this method can have the largest tolerance for program, bias variations. This methodology was successfully implemented in 0.18-mum triple self-aligned (SA3) split-gate cell characterization to provide program condition for 32 M products.
Novel single-poly EEPROM with damascene control-gate structure
(2005-10-01)
Sung, HC
;
Lei, TF
;
Hsu, TH
;
Wang, SW
;
Kao, YC
A novel single-poly EEPROM using damascene control gate (CG) structure is presented in this letter. The CG is tungsten (W) line made by a damascene process, and intergate dielectric is Al2O3 grown by atomic layer deposition (ALD). The program and erase mechanism is the same as the one for traditional stacked-gate cell, which uses the channel hot electron injection for programming and Fowler-Nordheim tunneling for channel erasing. With the high dielectric constant (K) property of Al2O3, we can perform the program and erase function with a voltage less than 6.5 V, which can be handled by 3.3 V devices instead of traditional high voltage devices. In the process compatibility aspect, this new cell needs only two extra masking steps over the standard CMOS process, and the high-kappa material is deposited in the back-end metallization steps without the contamination concerns on the front-end process. Therefore, this new technology is suitable for embedded application. In this letter, the good cell performance is demonstrated; such as, fast programming/erasing, good endurance and data retention.
Spherical harmonic analysis and synthesis using FFT: Application to temporal gravity variation
(2006-05-01)
Hwang, C
;
Kao, YC
;
土木工程學系
;
Department of Civil Engineering
FFT and complex algebra-based methods or spherical harmonic analysis and synthesis are presented. Two computer programs in FORTRAN are developed based on the methods. Both general and special cases are discussed. Special cases involve the analyses of gravity changes of the hydrological origin and the atmospheric origin. Functionals of the Earth's gravity field such as gravity anomaly and geoidal height can also be computed via synthesis. Thermal-corrected sea level anomaly from TOPEX/Poseidon and atmospheric pressure from ECMWF are used to compute changes of geopotential coefficients due to oceanic and atmospheric mass redistributions. Interesting phenomena in the changes of geopotential coefficients have been identified. The two computer programs can facilitate analyses and syntheses of gravity products from satellite missions such as GRACE. (c) 2005 Elsevier Ltd. All rights reserved.
Thermal stability of PVD TiN gate and its impacts on characteristics of CMOS transistors
(2001)
Wang, MF
;
Kao, YC
;
Huang, TY
;
Lin, HC
;
Chang, CY
The effects of rapid-thermal annealing (RTA) after source/drain (S/D) implant on the characteristics of CMOS transistors with sputtered TiN gate were investigated. Our results indicate that n(+)/p junctions need higher thermal budget than p(+)/n junctions to achieve low leakage performance. It was also found fron C-V measurements that the flat-band voltage and oxide thickness are both affected by the annealing treatment, especially for p-channel devices. A hump in the subthreshold characteristics of p-channel transistors is observed, owing to the existence of a leakage path along the isolation edge. It is also shown that agglomeration phenomenon is easier to incur during the high-temperature RTA step as the metal gate width becomes narrower. When this happens, gate oxide integrity would be degraded, resulting in increased gate leakage of n-channel transistors.