Browsing by Author "Kao, Yao-Huang"

Now showing 1 - 16 of 16

A design of image reject mixer for DTV tuner
(2005)
Kao, Yao-Huang
;
Yu, Ching-Jung
;
傳播研究所
;
Institute of Communication Studies
An image reject mixer of Hartley type for the digital TV tuner was designed. It consists of highly linear mixers, wide band polyphase filters, and an adder. The precise quadrature phase against process variation is specially focused. The rejection ratio is aimed at 30dB. The chip was fabricated by TSMC 0.25um 1P5M CMOS process.
A fully integrated spread spectrum clock generator using a dual-path loop filter
(2006)
Kao, Yao-Huang
;
Hsieh, Yi-Bin
;
傳播研究所
;
Institute of Communication Studies
A fully integrated spread spectrum clock generator (SSCG) using the VCO direct modulation was presented. The dual-path loop filter in the phased locked loop was employed to reduce the required area of capacitance in the filter by using another charge pump circuit. In the meantime, the third charge pump was used to achieve the triangle modulation. The proposed circuit had been fabricated by TSMC 0.35um CMOS single-poly quadruple-metal process. The clock rate from 50MHz to 480MHz with center spread spectrum ratios with 0.5%-2% was verified. The size of chip area was 0.82xO.8mm(2) including the loop filter and the power consumption was 27.5mW at 400MHz.
A fully integrated spread spectrum clock generator using two-point delta-sigma modulation
(2007)
Hsieh, Yi-Bin
;
Kao, Yao-Huang
;
傳播研究所
;
Institute of Communication Studies
A new spread spectrum clock generator (SSCG) using two-point delta-sigma modulation is presented in this paper. Not only the divider is varied, but also the voltage controlled oscillator is modulated. This technique can enhance the modulation bandwidth so that the effect of EMI suppression is improved. In addition, the method of two-path is applied to the loop filter to reduce the capacitance value such that the total integration can be achieved. The proposed SSG has been fabricated in a 0.35um CMOS process. The clock of 400MHz with center spread ratios of 1.25% and 2.5% are verified. The size of chip area is 0.90x0.89 mm(2).
A fully integrated spread-spectrum clock generator by using direct VCO modulation
(2008-08-01)
Hsieh, Yi-Bin
;
Kao, Yao-Huang
;
傳播研究所
;
Institute of Communication Studies
A compact architecture for a fully-integrated spread-spectrum clock generator (SSCG) using voltage-controlled oscillator direct modulation is presented in this paper. A dual-path loop filter in the phase-locked loop is employed to reduce the size of the capacitance in the filter with the aid of an extra charge pump and a unity gain amplifier. At the same time, a third-charge pump which generates triangular waves is used to perform the function of a spread-spectrum. The proposed circuit has been fabricated using a 0.35-mu m CMOS single-poly quadruple-metal process. The clock rate from 50 to 480 MHz with a center spread range of between 0.5 % and 2 % are verified and are close to the theoretical analyses. The size of the chip area is 0.82 x 0.8 mm(2) (including the loop filter) and the power consumption was 27.5 mW at 400 MHz. Index Terms-Phase-locked loop (PLL), spread-spectrum clock generator (SSCG).
A high performance spread spectrum clock generator using two-point modulation scheme
(2008-06-01)
Kao, Yao-Huang
;
Hsieh, Yi-Bin
;
傳播研究所
;
Institute of Communication Studies
A new spread spectrum clock generator (SSCG) using two-point delta-sigma modulation is presented in this paper. Not only the divider is varied, but also the voltage controlled oscillator is modulated. This technique can enhance the modulation bandwidth so that the effect of EMI suppression is improved with lower order Sigma Delta modulator and can simultaneously optimize the jitter and the modulation profile. In addition, the method of two-path is applied to the loop filter to reduce the capacitance value such that the total integration can be achieved. The proposed SSCG has been fabricated in a 0.35 mu m CMOS process. The clock of 400 MHz with center spread ratios of 1.25% and 2.5% are verified. The peak EMI reduction is 19.73 dB for the case of 2.5%. The size of chip area is 0.90 X 0.89 mm(2).
A Low Phase Noise CMOS Voltage-Controlled SAW Oscillator for OC-192 Applications
(2007-01-01)
Lin, Jon-Hong
;
Kang, Nai-Yuan
;
Kao, Yao-Huang
;
交大名義發表
;
National Chiao Tung University
A surface acoustic wave (SAW) resonator based oscillator was developed in response to OC-192 applications. The effects of parasitic capacitance were investigated. This oscillator was fabricated by tsmc 0.18 mu m CMOS process. The oscillator's white phase noise floor is -175 dBc/Hz for carrier offset frequency greater than 1 MHz and -136 dBc/Hz at 10 kHz carrier offset. The oscillator provides 4.0 dBm of output power and consumes 15mA from +1.2V DC power supply.
A Low Phase Noise CMOS Voltage-Controlled SAW Oscillator for OC-192 Applications
(2007-01-01)
Lin, Jon-Hong
;
Kang, Nai-Yuan
;
Kao, Yao-Huang
;
電信工程研究所
;
Institute of Communications Engineering
A surface acoustic wave (SAW) resonator based oscillator was developed in response to OC-192 applications. The effects of parasitic capacitance were investigated. This oscillator was fabricated by tsmc 0.18 mu m CMOS process. The oscillator's white phase noise floor is -175 dBc/Hz for carrier offset frequency greater than 1 MHz and -136 dBc/Hz at 10 kHz carrier offset. The oscillator provides 4.0 dBm of output power and consumes 15mA from +1.2V DC power supply.
A low phase noise voltage controlled SAW oscillator with surface transverse wave resonator for SONET application
(2005)
Lin, Jon-Hong
;
Kao, Yao-Huang
;
傳播研究所
;
Institute of Communication Studies
A surface transverse wave (STW) resonator based oscillator was developed in response to SONET OC-48 application. A high-Q STW resonator was designed and fabricated in the work. The oscillator's white phase noise floor is -170 dBc/Hz for carrier-offset frequency greater than 1 MHz. The oscillator's phase noise level of -67 dBc/Hz at 100 Hz carrier offset. The electronic frequency tuning range exceeds +/- 200 ppm.
A low phase-noise voltage-controlled SAW oscillator with surface transverse wave resonator for SONET application
(2007-01-01)
Lin, Jon-Hong
;
Kao, Yao-Huang
;
傳播研究所
;
Institute of Communication Studies
A surface transverse wave (STW) resonator-based oscillator was developed in response to SONET OC-48 application. To meet the low jitter objective, a high-Q STW resonator was designed and fabricated in this study. The residual phase-noise measurement techniques are used to evaluate the feedback oscillator components, such as the loop amplifier, STW resonator, and electronic phase shifter, which can play important roles in determining the oscillator's output phase-noise spectrum. The oscillator's white phase-noise floor is -170 dBc/Hz for carrier-offset frequency greater than 1 MHz. The oscillator's phase-noise level is -67 dBc/Hz at a 100-Hz carrier offset. Both low close-in phase-noise and low white phase-noise floor makes the oscillator meet low jitter requirement. The electronic frequency tuning range exceeds +/- 200 ppm. The oscillator provides 13.5 dBm of output power and consumes 65 mA from +5-V power supply.
A Low-Power and High-Precision Spread Spectrum Clock Generator for Serial Advanced Technology Attachment Applications Using Two-Point Modulation
(2009-05-01)
Kao, Yao-Huang
;
Hsieh, Yi-Bin
;
傳播研究所
;
Institute of Communication Studies
A new technique utilizing two-point (TP) modulation for a spread spectrum clock generator (SSCG) for serial advanced technology attachment is presented in which the divider ratio is varied by a digital Sigma Delta modulator, and the voltage-controlled oscillator is modulated analogically. With this technique, the modulation bandwidth is enhanced in order that the modulation profile accuracy and jitter performance caused by the Sigma Delta modulator can be improved at the same time. The order of the Sigma Delta modulator and the loop filter can be reduced to save power and area, while the electromagnetic interference (EMI) suppression still satisfies specifications. The dual-path loop filter (DL) reduces the size of the loop capacitor and enables full integration. The proposed TPDL-SSCG has been fabricated in a 0.18-mu m CMOS process. The size of the chip area is 0.44 x 0.48 mm(2). The circuit produces a clock of 1.5 GHz with a down-modulation ratio of 0.5%, 10.14 dB EMI of reduction, 5.485 ps rms jitter, and 35 ps peak-to-peak jitter. The power consumption, excluding an output buffer, is only 15.3 mW.
A new spread spectrum clock generator for SATA using double modulation schemes
(2007)
Hsieh, Yi-Bin
;
Kao, Yao-Huang
;
傳播研究所
;
Institute of Communication Studies
A new spread spectrum clock generator (SSCG) using double modulation is presented in this paper. Not only the divider is varied, but also the voltage controlled oscillator is modulated. This technique can enhance the modulation bandwidth so that the effect of EMI suppression is improved and can optimize the jitter caused by the Sigma Delta modulator. In addition, the method of two-path is applied to reduce the capacitance value such that the total integration can be achieved. The proposed SSCG has been fabricated in a 0.18um CMOS process. The clock of 1.5GHz with down spread ratio of 0.5% is realized for applications to serial ATA. The 19.63dB EMI reduction (RBW=10KHz) and 35ps-pp period jitter are achieved in this study. The size of chip area is 0.44x0.48mm(2). The power consumption is 27mW.
A wide input-range Sigma Delta modulator for applications to spread-spectrum clock generator
(2006)
Kao, Yao-Huang
;
Hsieh, Yi-Bin
;
傳播研究所
;
Institute of Communication Studies
A spread-spectrum clock generator (SSCG) using fractional-N phase-locked loop (PLL) with an extended range sigma-delta (EA) modulator is presented in this paper. The proposed EA modulator simply adds an extra output bit in the first stage modulator. It can enlarge the input range about three times as compared to the conventional modulator and solve the saturation problem when the input exceeds the boundary of the conventional modulator. The proposed SSCG has been fabricated in TSMC 0.35-um double-poly quadruple-metal CMOS process with output frequency of 300MHz. The active area is 0.63x4.62 mm(2) and the power consumption is 17.5mW.
Linear power amplifier with a modified predistortion compensation for NCDMA applications
(2005)
Kao, Yao-Huang
;
Chen, Wei-Chung
;
傳播研究所
;
Institute of Communication Studies
The selection of the matched transistor pair in a cascaded architecture for predistortion compensation is nontrivial. In this study, a modified architecture of predistortion with two paths is presented for the high power amplifier. The goal is to develop a IOW linear power amplifier with LDMOS transistor for 8 channels NCDMA repeater from 870 to 880MHz. With the modified scheme, the improvement of intermodulation is larger than 10dB and spurious is less than 50dBc.
Study of Front End of CMOS RFID Tag with Inductively-coupled Broadband Antenna
(2007)
Kao, Yao-Huang
;
Liu, Chia-Chuan
;
Kuo, Hung-Chang
;
電信工程研究所
;
Institute of Communications Engineering
Radio frequency identification (RFID) has received much attention. The ac to dc conversion efficiency is crucial for long range application in UHF band. The front end of the passive tag combined with the broadband antenna at 915MHz is investigated. Two subjects of high efficient charge-pump and antenna matching are focused. The chip is fabricated by TSMC 0.18um 1P6M CMOS. The antenna is on the 0.4mm FR4 pc board. With ten stages of capacitor-diode pair, the multiplier factor is 8.575 and dc voltage can reach to 3.4V and is regulated to 850mV with input power lies between 6 similar to 8dBm. Under matching, the communication range can reach to 4m.
Temperature Sensing by Using Film Bulk Acoustic Resonator at 2.4 GHz Band
(2009-11-01)
Kao, Yao-Huang
;
Lin, Jon-Hong
;
電信工程研究所
;
Institute of Communications Engineering
A four-layered film bulk acoustic resonator (FBAR) with an Al/AlN/SiN/Au composite structure was fabricated The FBAR is composed of a surface micromachined cantilever whose copper scarification layer is released by wet etching. A temperature coefficient (TC) of resonant frequency of -34 5 ppm/degrees C in the temperature range from 10 to 80 degrees C at 2 4 GHz is obtained. Using this resonator, an oscillator for temperature sensing was constructed, in which temperature can be detected easily by measuring the shift in oscillation frequency The TC of the oscillator is almost the same as that of the resonator. (C) 2009 The Japan Society of Applied Physics
Wireless Temperature Sensing using a Passive RFID Tag with Film Bulk Acoustic Resonator
(2008)
Lin, Jon-Hong
;
Kao, Yao-Huang
;
電信工程研究所
;
Institute of Communications Engineering
The lifetime of active RFID tag is limited by the equipped battery capacity. A passive RFID tag which gathers power via inductive coupling from RF power for temperature sensing was proposed to extend the lifetime of the tag. An oscillator with film bulk acoustic resonator (FBAR) ties at the heart of the tag. A four-layered FBAR with Al/AlN/SiN(x)/Au composite structure was fabricated. The oscillation frequency of the oscillator varies with the temperature linearly. The temperature can be detected easily by measuring the shift of oscillation frequency. The measured phase noise of the oscillator is -75dBc/Hz at 10 kHz offset. A linear temperature sensitivity of -34.5 ppm/degrees C in the temperature range from 10 and 80 degrees C at 2.48 GHz is achieved.