Browsing by Author "Kao, Yu-Hsiang"

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Cycle-Time-Aware Sequential Way-Access Set-Associative Cache for Low Energy Consumption
(2008)
Ting, Chih-Hui
;
Huang, Juinn-Dar
;
Kao, Yu-Hsiang
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we exploit the concept of sequential way access to reduce the number of ways being activated on each access of set-associative cache for low energy consumption while maintaining performance. The proposed architecture accesses each way in sequence, and then eliminates subsequent accesses if a hit is detected. It features smart cache placement and replacement policies to minimize the number of required access cycles. It can also reduce the heavy fanout load of the hit-signal, which suppresses the possible increase of cache cycle time due to more complicated cache control mechanism. The experimental results show that a 32KB 2-way sequential way-access set-associative cache reduces the energy consumption by 24% compared against a conventional 2-way set-associative cache with the same size at virtually no performance loss.
High-Performance NAND Flash Controller Exploiting Parallel Out-of-Order Command Execution
(2010)
Kao, Yu-Hsiang
;
Huang, Juinn-Dar
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
NAND flash memory is one of the most important components in modern non-volatile storage media. However, long command setup time and slow I/O interface frequency of current NAND flash device has been limiting the bandwidth of data transfer. In this paper, we propose a high-performance NAND flash controller architecture by exploiting two techniques parallel out-of-order execution of multi-die commands and two-plane address translation. By these two techniques, the number of commands being executed in parallel can be maximized and the average execution time per command can thus be greatly reduced to achieve higher performance. The experimental results show that the proposed NAND flash controller can improve the data access performance in both read and program for at least 18% as compared to a baseline NAND flash controller.