Browsing by Author "Ker, M. -D."

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Improvement on CDM ESD Robustness of High-Voltage Tolerant nLDMOS SCR Devices by Using Differential Doped Gate
(2014)
Chen, S. -H.
;
Linten, D.
;
Scholz, M.
;
Hellings, G.
;
Boschke, R.
Early failure has been observed during CDM ESD stress on high-voltage tolerant nLDMOS-SCR devices in a standard low-voltage CMOS technology due to the gate oxide (GOX) degradation. In this work, we propose a special p+/n+ differential doped gate which boosts the CDM ESD failure current level with a factor of 3 to 9.
Latchup in Bulk FinFET Technology
(2017-01-01)
Dai, C. -T.
;
Chen, S. -H.
;
Linten, D.
;
Scholz, M.
;
Hellings, G.
Latchup (LU) had been considered to be less important in advanced CMOS technologies. However, I/O interface and analog applications can still operate at high voltage (e.g., 1.8V or 3.3V) in sub-20nm bulk FinFET technologies. LU threats are never eliminated and the sensitivity towards LU is increased in bulk FinFET technology.