Browsing by Author "Ker, MD"

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A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC's
(1997-01-01)
Ker, MD
;
Chang, HH
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel electrostatic discharge (ESD) protection circuit, which combines complementary low-voltage-triggered lateral SCR (LVTSCR) devices and the gate-coupling technique, is proposed to effectively protect the thinner gate oxide of deep submicron CMOS IC's without adding an extra ESD-implant mask, Gate-coupling technique is used to couple the ESD-transient voltage to the gates of the PMOS-triggered/NMOS-triggered lateral silicon controlled rectifier (SCR) (PTLSCR/NTLSCR) devices to turn on the lateral SCR devices during an ESD stress, The trigger voltage of gate-coupled lateral SCR devices can be significantly reduced by the coupling capacitor, Thus, the thinner gate oxide of the input buffers in deep-submicron low-voltage CMOS IC's can be fully protected against ESD damage, Experimental results have verified that this proposed ESD protection circuit with a trigger voltage about 7 V can provide 4.8 (3.3) times human-body-model (HBM) [machine-model (MM)] ESD failure levels while occupying 47% of layout area, as compared with a conventional CMOS ESD protection circuit.
A new output buffer for 3.3-V PCI-X application in a 0.13-mu m 1/2.5-V
(2004)
Chen, SL
;
Ker, MD
;
電機學院
;
College of Electrical and Computer Engineering
An output buffer with low-voltage devices to driver high-voltage signals for PCI-X applications is proposed in this paper. Because PCI-X is a 3.3-V interface, the high-voltage gate-oxide stress is a serious problem to design PCI-X l/O circuits in a 0.13-mum 1/2.5-V CMOS process. The simulation results show that the proposed output buffer can be operated at 133 MHz without causing high-voltage gate-oxide stress problem in the 3.3-V P I-X interface. Besides, a level converter with only IN and 2.5-V devices that can converter 0/1-V voltage swing to 1/3.3-V voltage swing is also proposed in this paper. The testchip to verify this new proposed output buffer is now under fabrication. The measured results will be shown in the presentation.
A new Schmitt trigger circuit in a 0.13-mu m 1/2.5-V CMOS process to receive 3.3-V input signals
(2005-07-01)
Chen, SL
;
Ker, MD
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new Schmitt trigger circuit, which is implemented by low-voltage devices to receive the high-voltage input signals without gate-oxide reliability problem, is proposed. The new proposed circuit, which can be operated in a 3.3-V signal environment without suffering high-voltage gate-oxide overstress, has been fabricated in a 0.13-mu m 1/2.5-V 1P8M CMOS process. The experimental results have confirmed that the measured transition threshold voltages of the new proposed Schmitt trigger circuit are about 1 and 2.5 V, respectively. The new proposed Schmitt trigger circuit is suitable for mixed-voltage input-output interfaces to receive input signals and reject input noise.
A novel LC-Tank ESD protection design for giga-Hz RF circuits
(2003)
Ker, MD
;
Chou, CI
;
Lee, CM
;
電機學院
;
College of Electrical and Computer Engineering
To further decrease the power gain loss and noise figure of RF LNA circuit from the on-chip ESD protection circuit. A novel LC-tank RF ESD protection circuits is proposed in this paper and has been successfully verified in a 0.25-mum CMOS process with top thick metal. With the resonance of LC-tank, the LC-tank RF ESD protection circuit can reduce the power gain loss and noise figure at the operation frequency from ESD device. From the experimental results, the 4.5 circles inductor of LC-tank is the best choice for the requirement of 2kV HBM ESD level. The proposed LC-tank ESD protection circuit will be one of the most effective ESD protection solutions for RF circuits in higher frequency band (>10GHz).
Abnormal ESD failure mechanism in high-pin-count BGA packaged ICs due to stressing nonconnected balls
(2004-03-01)
Lo, WY
;
Ker, MD
;
電機學院
;
College of Electrical and Computer Engineering
An abnormal failure mechanism due to ESD pulse applied on the nonconnected (NC) solder balls of a high-pin-count (683 balls) BGA packaged chipset IC is presented. The ESD test results of the IC product were found below human-body-model (HBM) 2 kV when stressing all balls or only stressing NC balls, but above HBM 3 kV when stressing all balls excluding NC balls. Failure analyses, including scanning electron microscopy (SEM) photographs and the measurement of current waveforms during ESD discharging event, have been performed. With a new proposed equivalent model, a clear explanation on this unusual phenomenon is found to have a high correlation to the small capacitor method (SCM). Several solutions to overcome this failure mechanism are also discussed.
Active device under bond pad to save I/O layout for high-pin-count SOC
(2003-01-01)
Ker, MD
;
Peng, JJ
;
Jiang, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
To save layout area for electrostatic discharge (ESD) protection design in the SOC era, test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35-mum one-poly-four-metal (1P4M) 3.3V CMOS process for verification. The bond pads had been drawn with different layout patterns on the inter-layer metals to investigate the effect of bonding stress on the active devices under the pads. Threshold voltage, off-state drain current, and gate leakage current of these devices under bond pads have been measured. After assembled in wire bond package, the measurement results show that there are only little variations between devices under bond pads and devices beside bond pads. This result can be applied on saving layout area for on-chip ESD protection devices or I/O devices of IC products, especially for the high-pin-count system-on-a-chip (SOC).
Active electrostatic discharge (ESD) device for on-chip ESD protection in sub-quarter-micron complementary metal-oxide semiconductor (CMOS) process
(2004-01-15)
Ker, MD
;
Tseng, TK
;
電機學院
;
College of Electrical and Computer Engineering
A novel electrostatic discharge (ESD) protection device with a threshold voltage of similar to0V for complementary metal-oxide semiconductor (CMOS) integrated circuits in sub-quarter-micron CMOS technology is proposed. Quite different to the traditional ESD protection devices, such an active ESD device is originally standing in its turn-on state when the IC is zapped under ESD events. Therefore, such an active ESD device has the fastest turn-on speed and the lowest turn-on voltage to effectively protect the internal circuits with a much thinner gate oxide in future sub-0.1 mum CMOS technology. The proposed active ESD device is fully process-compatible to the general sub-quarter-micron CMOS process.
Analysis and prevention on NC-ball induced ESD damages in a 683-pin BGA packaged chipset IC
(2003-09-01)
Lo, WY
;
Ker, MD
;
電機學院
;
College of Electrical and Computer Engineering
An abnormal failure mechanism due to ESD zapping on the Non-Connected (NC) balls of a 683-pin BGA packaged chipset IC is presented. Failure analyses, including Scanning Electronic Microscopy (SEM) photographs and the measurement of current waveforms during ESD zapping, had been performed with a new proposed equivalent circuit to give clear explanation on this unusual phenomenon. Several methods to prevent such failure mechanism are also discussed. (C) 2003 Elsevier Ltd. All rights reserved.
Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process
(2003-08-01)
Chen, TY
;
Ker, MD
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The layout dependence on ESD robustness of P40S and PMOS devices has been experimentally investigated in details. A lot of CMOS devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated to find the optimized layout rules for electrostatic discharge (ESD) protection. The main layout parameters to affect ESD robustness of CMOS devices are the channel width, the channel length, the clearance from contact to poly-gate. edge at drain And source regions, the. spacing from,the drain diffusion to the guardring diffusion, and the finger width of each unit finger. Non-uniform turn-on effects have been clearly investigated in, the gate-grounded large-dimension NMOS devices by using EMMI (EMission MIcroscope) observation. The optimized layout parameters have been verified to effectively improve ESD robustness of CMOS devices. The relations between. ESD robustness and the layout parameters have been explained by both transmission line pulsing (TLP) measured data and the, energy band diagrams.
Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product
(2003-08-01)
Lin, IC
;
Huang, CY
;
Chao, CJ
;
Ker, MD
;
電子工程學系及電子研究所
Latchup failure induced by electrostatic discharge (ESD) protection circuits occurred anomalously in a high-voltage IC product. Latchup issues existed at only three output pins, two of which belonged to the top and the other to the side. The layouts of top and bottom output pins are identical, and side output pins have another identical layouts. In our experiments it was found latchup of two top output pins were originated from the latchup of the side output pin, and therefore heat-induced latchup aggravation issue must be noticed during latchup test. Furthermore, large power line current (Idd) existed during triggering this side output pin and led to subsequent latchup. After thorough layout inspection, the layout of this side output pin is identical to all other side output pins except that it has an additional N-well (NW) resistor of gate-triggered high-voltage PMOS beside. It was later proved by engineering experiments that this NW resistor is the origin of inducing latchup in this product, and a new mechanism was proposed for this latchup failure. Improvements and solutions were also provided to successfully solve the latchup issues of these three output pins. (C) 2003 Elsevier Ltd. All rights reserved.
Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's
(2001)
Ker, MD
;
Jiang, HC
;
Peng, JJ
;
Shieh, TL
;
電子工程學系及電子研究所
A program methodology is proposed to automatically place the guard rings in the chip layout to improve latchup immunity of the CMOS IC's. The additional guard rings between the I/O cells and the internal circuits had been practically proven to significantly increase the latchup immunity of CMOS IC's. Therefore, the layout spacing from the I/O cells to the internal circuits can be reduced to a reasonable distance to save the total chip size. In this paper, a "Guard Ring Automation" program to realize the additional guard rings in the layout is proposed to make the layout more automatically and accurately.
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
(1996-09-01)
Ker, MD
;
Wu, CY
;
Cheng, T
;
Chang, HH
;
電子工程學系及電子研究所
Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed, The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-couple efficiency of this proposed ESD protection circuit, Using this capacitor-couple ESD protection circuit, the thinner gate oxide of CMOS devices in deep-submicron low-voltage CMOS ASIC can be effectively protected.
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
(1996-09-01)
Ker, MD
;
Wu, CY
;
Cheng, T
;
Chang, HH
;
電子工程學系及電子研究所
Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed, The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-couple efficiency of this proposed ESD protection circuit, Using this capacitor-couple ESD protection circuit, the thinner gate oxide of CMOS devices in deep-submicron low-voltage CMOS ASIC can be effectively protected.
Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger
(2000-03-01)
Ker, MD
;
Chang, HH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The lateral SCR devices used in CMOS on-chip ESD protection circuits are reviewed. Such SCR devices had been found to be accidentally triggered by noise pulses when the ICs are operated in the application systems. A cascoded design is therefore proposed to safely apply the LVTSCR devices for whole-chip ESD protection in CMOS ICs without causing unexpected operation errors or latchup danger. The temperature dependence on the holding voltage of the cascoded LVTSCRs has been investigated in detail. From the experimental verification, the cascoded LVTSCRs can be fully turned on within a time below 20 ns. The ESD robustness per layout area of the three-cascoded LVTSCRs can be 0.83 V/mu m(2) in a 0.35-mu m silicide CMOS process without using the extra silicide-blocking and ESD-implant masks, whereas the ESD robustness of the gate-grounded NMOS is only 0.25 V/mu m(2). Such cascoded LVTSCRs with a tunable holding voltage greater than VDD can provide CMOS ICs with effective component-level ESD protection but without causing catchup danger if it is accidentally triggered by the system-level overshooting or undershooting noise pulses. (C) 2000 Elsevier Science Ltd. All rights reserved.
Characterization on ESD devices with test structures in silicon germanium RF BiCMOS process
(2004)
Ker, MD
;
Wu, WL
;
Chang, CY
;
電機學院
;
College of Electrical and Computer Engineering
Different electrostatic discharge (ESD) devices in a 0.35-mum silicon germanium (SiGe) RF BiCMOS process are characterized in detail by transmission line pulse (TLP) generator and ESD simulator for on-chip ESD protection design. The test structures of diodes with different p-n junctions and the silicon-germanium heterojunction bipolar transistors (HBTs) with different layout parameters have been drawn for investigating their ESD robustness. The human-body-model (HBM) ESD robustness of SiGe HBTs with the optional low-voltage (LV), ligh-voltage (HV), and high-speed (HS) implantations has been measured and compared in the experimental test chips.
CMOS chip as luminescent sensor for biochemical reactions
(2003-06-01)
Lu, U
;
Hu, BCP
;
Shih, YC
;
Yang, YS
;
Wu, CY
We describe a novel biochemical sensing method and its potential new biosensing applications. A light-sensitive complementary metal oxide semiconductor (CMOS) chip prepared through a standard 0.5-mum CMOS process was developed for measuring biochemical reactions. A light producing enzymatic reaction catalyzed by horseradish peroxidase (HRP) was designed as a platform reaction to determine the concentration of hydrogen. peroxide (H2O2) by the CMOS chip with a standard semiconductor parameter analyzer (HP4145). The kinetics of enzymatic reaction were determined and compared with a standard and sophisticated fluorometer (Hitachi F-4500) in a biochemical laboratory. Similar results were obtained by both instruments. Using glucose oxidase as an example, we further demonstrated that the HRP platform can be used to determine other H2O2 producing reactions with the CMOS system. The result points to an important application of the CMOS chip in biological measurements and in diagnosis of various health factors.
Compact layout rule extraction for latchup prevention in a 0.25-mu m shallow-trench-isolation silicided bulk CMOS process
(2001)
Ker, MD
;
Lo, WY
;
Chen, TY
;
Tang, H
;
Chen, SS
An experimental extraction to find the area-efficient compact layout rules to prevent latchup in bulk CMOS IC's is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances. A new efficient latchup prevention design, by adding the additional internal guard rings between the I/O cells and the internal core circuits, has been successfully proven in a 0.25-mum shallow-trench-isolation (STI) silicided bulk CMOS process. Through detailed experimental verification including temperature effect, the proposed extraction method to define compact layout rules has been established to save the silicon area of CMOS IC's, but still to maintain high enough latchup immunity in bulk CMOS IC's.
Complementary substrate-triggered SCR devices for on-chip ESD protection circuits
(2002)
Ker, MD
;
Hsu, KC
;
電機學院
;
College of Electrical and Computer Engineering
The turn-on mechanism of SCR device is essentially a current triggering event. While a current is applied to the base or substrate of a SCR device, it can be quickly triggered on into its latching state. In this paper, the complementary substrate-triggered SCR devices which are combined with the substrate-triggered technique and SCR devices, are first reported in the literature for using in the on-chip ESD. protection circuits. A complementary style on the substrate-triggered SCR devices is designed to discharge both of the positive and negative ESD stresses on the pad. The total holding voltage of the substrate-triggered SCR device can be increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices for the I/O pad and power pad have been successfully verified in a 0.25-mum STI CMOS process with the HBM (MM) ESD level of >8kV (650V) in a small layout area.
Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI
(1996-04-01)
Ker, MD
;
Wu, CY
;
Chang, HH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
There are one LVTSCR device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in complementary style to offer effective and direct ESD discharging paths from the input or output pads to VSS and VDD power lines, The trigger voltages of LVTSCR devices are lowered to the snapback-breakdown voltages of short-channel NMOS and PMOS devices. This complementary-LVTSCR ESD protection circuit offers four different discharging paths to one-by-one bypass the four modes of ESD stresses at the pad, so it can effectively avoid the unexpected ESD damages on internal circuits, Experimental results show that it can perform excellent ESD protection capability in a smaller layout area as compared to the conventional CMOS ESD protection circuit, The device characteristics under high-temperature environment of up to 150 degrees C is also experimentally investigated to guarantee the safety of this proposed ESD protection circuit.
Correlation between transmission-line-pulsing I-V curve and human-body-model ESD level on low temperature poly-Si TFT devices
(2004)
Ker, MD
;
Hou, CL
;
Chang, CY
;
Chu, FT
;
電機學院
The relations between human-body-model (HBM) electrostatic discharge (ESD) waveform and transmission line pulsing (TLP) I-V curve on low temperature poly-Si (LTPS) thin film transistor (TFT) have been investigated in this paper. By using ESD zapper and TLP system, the ESD waveforms and TLP I-V curves on the LPTS TFT devices under different device dimensions have been measured. From the experimental results, the turn-on resistances of TFT devices during HBM zapping and TLP stress are almost the same. Such experimental results have shown a good correction between HBM ESD level and TLP measurement on LTPS TFT devices.