Browsing by Author "Kim, Jae-Joon"

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Impact of NBTI and PBTI in SRAM Bit-cells: Relative Sensitivities and Guidelines for Application-Specific Target Stability/Performance
(2009)
Bansal, Aditya
;
Rao, Rahul
;
Kim, Jae-Joon
;
Zafar, Sufi
;
Stathis, James H.
The stability and performance characteristics of Static Random Access Memories (SRAMs) are known to degrade with time due to the impact of Negative and Positive Bias Temperature Instabilities (NBTI (in PFET) and PBTI (in NFET)). In this work, we provide insights into relative sensitivities of these phenomena on speed and stability of SRAM cells. Relative impact on access time, stability, and tolerability of one phenomenon over another has been studied for different application specific (high-performance or low-power) SRAM cells. We show that high-performance SRAM cells should have lower V-T drift due to PBTI compared with dense cells to contain READ stability and access time. Further, worst-case static stress poses tighter process constraints compared with alternating stress.
Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability
(2009-06-01)
Bansal, Aditya
;
Rao, Rahul
;
Kim, Jae-Joon
;
Zafar, Sufi
;
Stathis, James H.
Negative and Positive Bias Temperature Instabilities (NBTI (in PFET) and PBTI (in NFET)) weaken MOSFETs with time. The impact of such device degradation can be severe in Static Random Access Memories (SRAMs) wherein stability is governed by relative strengths of FETs. Degradation in stability with time under 'worst case condition' gets more important because of reduced guard-banding due to process induced instability. In this work, circuit insights into worst-case conditions and effect of NBTI and PBTI, individually and in combination, on the stability of an SRAM cell are presented. It is shown that measurable quantities such as static noise-margin are not sufficient to completely understand the combined effect of NBTI and PBTI Monte-Carlo simulations are performed in a 45 nm PDSOI technology to estimate the increase in cell failure probability with time. In worst case, NBTI and PBTI both degrade read stability (significantly) and writability, (marginally). Further, we analyze the choice of optimal power supply considering the trade-off between short-term stability (due to process variations) and long-term stability (due to NBTI/PBTI) to achieve six-sigma confidence in SRAM cell robustness. (C) 2009 Elsevier Ltd. All rights reserved.
Ring oscillator circuit structures for measurement of isolated NBTI/PBTI effects
(2008)
Kim, Jae-Joon
;
Rao, Rahul
;
Mukhopadhyay, Saibal
;
Chuang, Ching-Te
;
交大名義發表
Simple ring-oscillator circuit has been used to estimate the degradation in circuit performance due to negative bias temperature instability (NBTI) effect but it fails to isolate the degradation from the NBTI for PMOS and the positive bias temperature instability (PBTI) for NMOS in high-K dielectric/metal gate CMOS technology. In this paper, we propose new circuit structures which monitor the NBTI and the PBTI effects separately while conserving the simplicity and efficiency of a ring oscillator based circuit. We also show that the proposed circuits have better sensitivity to the NBTI effect than conventional ring-oscillator circuit when they are used in technologies that experience negligible PBTI effect.
Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection
(2013-09-01)
Ghosh, Amlan
;
Rao, Rahul M.
;
Kim, Jae-Joon
;
Chuang, Ching-Te
;
Brown, Richard B.
The need for efficient and accurate detection schemes to assess the impact of process variations on the parametric yield of integrated circuits has increased in the nanometer design era. In this paper, the difference of rise and fall slew is presented as another process-variation metric along with the delay in determining the relative mismatch between the drive strengths of nMOS and pMOS devices. The importance of considering both of these metrics is illustrated, and a new slew-rate monitoring circuit is presented for measuring the difference of rise and fall slew of a signal on the critical path of a circuit. Sensitivity analysis with multiple pulses as input has also been investigated. Bias generator circuits that track nMOS and pMOS threshold voltages have been incorporated, which makes the design less susceptible to process variation. Design considerations, simulation results, and characteristics of the slew-rate monitor circuitry in a 65-nm IBM CMOS process are presented, and a sensitivity of 50 MHz/50 ps for single pulse input is achieved. The measurement sensitivity of a fabricated slew-rate monitor in a 65-nm IBM CMOS technology is 0.11 V/mu s, with 1089 pF as the output load of the slew-rate monitor.
SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage
(2011-01-01)
Mukhopadhyay, Saibal
;
Rao, Rahul M.
;
Kim, Jae-Joon
;
Chuang, Ching-Te
;
交大名義發表
Increasing variations in device parameters significantly degrades the write-ability of SRAM cells in deep sub-100 nm CMOS technology. In this paper, a transient negative bit-line voltage technique is presented to improve write-ability of SRAM cell. Capacitive coupling is used to generate a transient negative voltage at the low-going bit-line during Write operation without using any on-chip or off-chip negative voltage source. Statistical simulations in a 45-nm PD/SOI technology show a 10(3) X reduction in the Write-failure probability with the proposed method.
SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage
(2011-01-01)
Mukhopadhyay, Saibal
;
Rao, Rahul M.
;
Kim, Jae-Joon
;
Chuang, Ching-Te
;
交大名義發表
Increasing variations in device parameters significantly degrades the write-ability of SRAM cells in deep sub-100 nm CMOS technology. In this paper, a transient negative bit-line voltage technique is presented to improve write-ability of SRAM cell. Capacitive coupling is used to generate a transient negative voltage at the low-going bit-line during Write operation without using any on-chip or off-chip negative voltage source. Statistical simulations in a 45-nm PD/SOI technology show a 10(3) X reduction in the Write-failure probability with the proposed method.