Browsing by Author "Ko, C. T."

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BCB-to-oxide bonding technology for 3D integration
(2012-02-01)
Lin, S. L.
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Huang, W. C.
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Ko, C. T.
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Chen, K. N.
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電子工程學系及電子研究所
Process optimization of BCB polymer to silicon oxide bonding was investigated. The suitable bonding temperature is about 300 degrees C, while bond failure of BCB-to-oxide bonding is observed starting from 400 degrees C. Bonding interface morphologies and bond strengths of BCB-to-oxide bonding were investigated as well. PECVD oxide to BCB bonding has better bonding quality than that of thermal oxide to BCB bonding. Si-O-Si bonds may be the reason of a strong BCB to oxide bonding. Water molecules link BCB and oxide surfaces during the initial contact, while Si-O-Si bonds are formed during bonding. This proposed mechanism of BCB-to-oxide bonding provides a guideline for polymer to oxide hybrid bonding technology in 3D integration. (C) 2011 Elsevier Ltd. All rights reserved.
Bonding Temperature Optimization and Property Evolution of SU-8 Material in Metal/Adhesive Hybrid Wafer Bonding
(2011-08-01)
Chen, K. N.
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Cheng, C. A.
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Huang, W. C.
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Ko, C. T.
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電子工程學系及電子研究所
Bonding temperature optimization of SU-8 material for metal/adhesive hybrid bonding was investigated. The good bond quality of SU-8 adhesive can be achieved with the bonding temperature between 150 degrees C and 250 degrees C, while bond failures of SU-8 wafers are observed starting from 275 degrees C. IR transmittance spectra measurements indicate the crosslinks inside SU-8 break and further bond failure is observed due to the large decomposition of epoxy rings and phenyl in plane bending above 275 degrees C. This research provides guidelines of material selection and bonding parameters for heterogeneous integration, 3DIC and MEMS applications using metal/adhesive hybrid bonding.
Electrical Performances and Quality Investigations of Integrated Bonded Structures and TSVs for 3D Interconnects
(2012)
Chen, K. N.
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Chang, Y. J.
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Ko, C. T.
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Hsu, S. Y.
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Chen, H. Y.
Structural Design, Process, and Reliability of a Wafer-Level 3D Integration Scheme with Cu TSVs Based on Micro-bump/Adhesive Hybrid Wafer Bonding
(2012)
Ko, C. T.
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Hsiao, Z. C.
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Chang, Y. J.
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Chen, P. S.
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Huang, J. H.
In this study, a wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding is demonstrated. To realize the signal transmission effects in high speed digital signaling via Cu TSV and Cu/Sn micro-joint interconnection, the insertion loss was investigated by simulation analysis with variable TSV pitches, micro-bump diameters and chip thicknesses. Key technologies include TSV fabrication, micro-bumping, hybrid scheme making, hybrid bonding, wafer thinning and backside RDL formation were well developed and integrated to perform the 3D integration scheme. 5 mu m TSV, 10 mu m microbump, 20 mu m pitch, 40 mu m thin wafer, and 250 degrees C low temperature W2W hybrid bonding have been successfully integrated in the integration platform. The 3D scheme was characterized and assessed to have excellent electrical performance and reliability, and is potentially to be applied for 3D product applications.