Browsing by Author "Ko, Cheng-Ta"

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A Novel 3D Integration Scheme for Backside Illuminated CMOS Image Sensor Devices
(2014-06-01)
Ko, Cheng-Ta
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Hsiao, Zhi-Cheng
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Chang, Hsiang-Hung
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Lyu, Dian-Rong
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Hsu, Chao-Kai
A novel backside-illuminated CMOS image sensor (BSI-CIS) scheme and process are developed and demonstrated. This innovative scheme can be realized without fusion oxide bonding and through-silicon via (TSV) fabrication. This wafer-level TSV-less BSI-CIS scheme includes transparent ultrathin silicon (similar to 3.6 mu m) and uses several bonding technologies. The characterization and assessment results indicate that the integration scheme possesses excellent electrical integrity and reliability. In addition, good quality results of the image functional test demonstrate the excellent performance of this scheme. This novel scheme also provides a realizable low-cost solution for the next-generation CIS and further 3-D novel BSI-CIS scheme.
A Wafer-Level Three-Dimensional Integration Scheme With Cu TSVs Based on Microbump/Adhesive Hybrid Bonding for Three-Dimensional Memory Application
(2012-06-01)
Ko, Cheng-Ta
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Hsiao, Zhi-Cheng
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Chang, Yao-Jen
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Chen, Peng-Shu
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Hwang, Yu-Jiau
Thin wafer/chip stacking with vertical interconnect by a Cu through-silicon via (TSV) and a Cu/Sn microjoint is one of the candidates for 3-D integration. The insertion loss of the two-chip stack was evaluated with different TSV pitches, microbump diameters, and chip thicknesses to realize the signal transmission effects in high-speed digital signaling via TSV and microjoint interconnection. In addition, a wafer-level 3-D integration scheme with Cu TSVs based on Cu/Sn microbump and BCB adhesive hybrid bonding was demonstrated. Key technologies, including TSV interconnection, microbumping, hybrid bonding, wafer thinning, and backside RDL formation, were well developed and integrated to realize 3-D integration. This paper presents a complete study of the structure design, the process condition, and the electrical and reliability assessment of the wafer-level 3-D integration scheme. This 3-D integration scheme with excellent electrical performance and reliability provides a promising solution for 3-D memory application.
Adhesion Investigation Between Metal and Benzocyclobutene (BCB) Polymer Dielectric Materials in 3-D Integration Applications
(2014-09-01)
Shih, Jian-Yu
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Huang, Wen-Chun
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Ko, Cheng-Ta
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Yang, Zheng
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Hu, Sheng-Hsiang
In this paper, the interfacial adhesion strength between metal layer and benzocyclobutene (BCB) polymer dielectric in 3-D integration applications is investigated. The effects of layer thickness, layer stacking order, and additional adhesion layer of titanium (Ti) layer between copper (Cu) and BCB polymer are investigated. Surprisingly, the conventional titanium adhesion layer commonly used in the semiconductor industry weakens the interfacial adhesion strength between copper and BCB. Additionally, to figure out the interfacial adhesion mechanisms, the interfacial structures probed by sum-frequency-generation vibrational spectroscopy are correlated to the adhesion strengths measured from corresponding sample interfaces. It is found that ordered C-H groups at the metal/BCB interface, such as titanium/BCB or molybdenum/BCB, lead to weak interfacial adhesion strength, whereas disordered interfaces, i.e., copper/BCB, lead to strong interfacial adhesion strength.
Adhesive Selection and Bonding Parameter Optimization for Hybrid Bonding in 3D Integration
(2012-03-01)
Chen, Kuan-Neng
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Ko, Cheng-Ta
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Hsiao, Zhi-Cheng
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Fu, Huan-Chun
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Lo, Wei-Chung
Hybrid bonding, an emerging bonding approach with high yield and reliability, can achieve vertical interconnection with adhesive serving reinforcement of the mechanical stability between stacked ICs. To develop metal/adhesive hybrid bonding technology, four kinds of polymer materials, BOB, SU-8, AL-Polymer, and PI, were evaluated as the bonding adhesive. The compatibility between each polymer and metal was investigated, and the application range of each material was established thereof. Furthermore, the scheme of Cu-Sn-Cu interconnection hybridized with patterned BCB was designed and evaluated. Two key factors were discussed and optimized to perform the bonding integrity. The evaluation results and successful metal/adhesive hybrid bonding demonstration are disclosed in the paper.
An RDL-First Fan-Out Panel-Level Package for Heterogeneous Integration Applications
(2019-01-01)
Lin, Yu-Min
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Wu, Sheng-Tsai
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Wang, Chun-Min
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Lee, Chia-Hsin
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Huang, Shin-Yi
Technologies of Fan-outpanel-level packaging (FOPLP) are studies in this paper. First, the warpage control of a molded panel is a crucial problem for FOWLP technology development. In this paper, finite element analysis (FEA) is applied to study the influence of back end of the line (BEOL) process-induced warpage, as well as characterization for simulation, and investigation of each single process. In our process, a liquid release material is coated onto a 370 mm x 470 mm glass carrier. After baking, three layers of redistribution layer (RDL), passivation, and Cu leads are fabricated on the panel with coating, exposing, developing, lithography, and electroplating processes. Silicon test chips with a size of 16 mm x 10 mm and micro solder bumps with a pitch of 90 mu m are thinned down to 150 mu m. Test chips are then flip-chip bonded onto glass carrier with pre-bond and reflow proces. After panel molding, a laser debonding method, another key technology advancement, is utilized for panel debond. Debond performance, which is directly related to laser parameter and panel-level package (PLP) structure, is critical. After debonding, the molded panel is cleaned, followed by dicing and OSP coating processes, and then the electrical performance of the interconnection is evaluated. Reliability tests at the component level, such as pre-condition, thermal cycling test (TCT), and unbiased HAST (uHAST), are performed. The demonstration of RDL-first PLP technology without interposers proves its great potential in heterogeneous integration applications.
Backside-Process-Induced Junction Leakage and Process Improvement of Cu TSV Based on Cu/Sn and BCB Hybrid Bonding
(2013-03-01)
Chang, Yao-Jen
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Ko, Cheng-Ta
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Yu, Tsung-Han
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Chiang, Cheng-Hao
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Chen, Kuan-Neng
Wafer-level 3-D integration using Cu through-silicon vias (TSVs) and fine-pitch Cu/Sn-BCB hybrid bonding is investigated with electrical leakage current. With the well-fabricated Cu TSVs and Cu/Sn bond structures, the leakage current path in this scheme due to backside process was found, and the corresponding mechanism is discussed. The leakage current can be solved by the modified backside process. The improved 3-D integration scheme shows extremely low leakage current and no visible defects inside Cu TSV.
Breakthrough in Cu to Cu Pillar-Concave Bonding on Silicon Substrate with Polymer Layer for Advanced Packaging, 3D, and Heterogeneous Integration
(2017-01-01)
Yang, Yu-Tao
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Yu, Ting-Yang
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Kuo, Shu-Chiao
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Huang, Tai-Yuan
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Yang, Kai-Ming
In this paper, finite element method (FEM) simulations are carried out with pillar-concave structure using silicon substrate, silicon substrate with polyimide (PI) and with polybenzoxazole (PBO) for realization of Cu-Cu bonding at low temperature. Parameters of bonding temperature, pillar diameter, concave sidewall angle, and multilayer of concave structure are all considered in simulation. In addition, pillarconcave bonding is successfully demonstrated on silicon substrates with bonding temperatures ranging from 60 degrees C to 100 degrees C. Simulation and fabrication results of concept show potential impacts on current semiconductor packaging method with advantages such as high adhesive strength of polymer on various types of substrates, simplified manufacturing process, solder free interconnect and packaging process, Cu-Cu direct bonding at temperature lower than 100 degrees C, and high tolerance in surface roughness.
Electrical and Reliability Investigation of Cu TSVs With Low-Temperature Cu/Sn and BCB Hybrid Bond Scheme
(2013-01-01)
Chang, Yao-Jen
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Ko, Cheng-Ta
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Chen, Kuan-Neng
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A wafer-level 3-D integration scheme using Cu through-silicon vias (TSVs) and fine-pitch Cu/Sn-BCB hybrid bonding was developed and investigated with electrical characterization and reliability assessment. The hybrid bonding could be achieved below 250 degrees C. Low Kelvin resistance and stable daisy chain resistance were achieved in 5- and 10-mu m TSV test structures across the whole wafer. Without obvious deterioration in reliability test results, the integrated Cu TSV and hybrid bond scheme can be potentially designed for 3-D integration applications.
Electrical Investigation and Reliability of 3D Integration Platform using Cu TSVs and Micro-Bumps with Cu/Sn-BCB Hybrid Bonding
(2013)
Chang, Yao-Jen
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Ko, Cheng-Ta
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Hsiao, Zhi-Cheng
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Chiang, Cheng-Hao
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Fu, Huan-Chun
In this paper, the wafer-level three-dimensional (3-D) integration scheme using copper TSVs and fine-pitch Cu/Sn-BCB hybrid bonding is designed, fabricated, and completely investigated on electrical characteristics and stability. Key technologies in this 3D integration scheme include high aspect-ratio Cu TSV, fine-pitch Cu/Sn micro-bumps, 250 degrees C low temperature hybrid bonding, wafer thinning and backside RDL formation. The Kelvin and leakage current structures are designed for realization of fundamental electrical properties, and the daisy chain feature is designed for stability evaluation with several reliability tests. All the samples pass the 1000-cycle thermal cycling test, humidity test, and multiple AC current stressing. This scheme shows a significant leakage current improvement after modifying backside process. The stable reliability results and excellent electrical characteristics indicate that the 3D integration scheme has the excellent sealing ability against oxidation and corrosion, and could be potentially applied for future mass production.
Investigation of Pillar-Concave Structure for Low-Temperature Cu-Cu Direct Bonding in 3-D/2.5-D Heterogeneous Integration
(2020-08-01)
Chou, Tzu-Chieh
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Yang, Kai-Ming
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Li, Jian-Chen
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Yu, Ting-Yang
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Yang, Yu-Tao
With the advantage of high surface-roughness tolerance, the pillar-concave Cu-Cu direct bonding without chemical-mechanical planarization (CMP) is investigated in detail, including the mechanism of thermal compensation, analysis of roughness, bonding strength, and bonding reliability. With the special design of Cu bond structure, excellent bonding results can be achieved under low thermal budget (150 degrees C for 1 min, atmosphere) with even high roughness of bonding surface. In addition, the pillar-concave scheme applied to fan-out panel-level package (FOPLP) has been demonstrated, showing the high feasibility of this scheme to realize applications in heterogeneous integration.
Low temperature bonding technology for 3D integration
(2012-02-01)
Ko, Cheng-Ta
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Chen, Kuan-Neng
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
3D integration provides a promising solution to achieve system level integration with high function density, small form factor, enhanced transmission speed and low power consumption. Stacked bonding is the key technology to enable the communication between different strata of the 3D integration system. Low temperature bonding approaches are explored in industry to solve the performance degradation issue of the integrated devices. In this paper, various low temperature bonding technologies are reviewed and introduced, as well as the latest developments in world-wide companies and research institutes. The outlook for industrial application is also addressed in the paper. (C) 2011 Elsevier Ltd. All rights reserved.
Low Temperature Cu-Cu Gang Bonding for RDL-First Fan-Out Panel Level Package
(2019-01-01)
Yang, Kai-Ming
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Chou, Tzu-Chieh
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Ko, Cheng-Ta
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Lin, Chen-Hao
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Chen, Yu-Hua
In this paper, low temperature (190-220 degrees C) Cu-Cu gang bonding at a low vacuum pressure is demonstrated. The low temperature technologies can be applied to the RDL-first Fan-Out panel level package (FOPLP).
Low-Temperature Cu-Cu Direct Bonding Using Pillar-Concave Structure in Advanced 3-D Heterogeneous Integration
(2017-09-01)
Yang, Yu-Tao
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Chou, Tzu-Chieh
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Yu, Ting-Yang
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Chang, Yu-Wei
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Huang, Tai-Yuan
Low-temperature Cu-Cu bonding utilizing pillar and concave on silicon substrate with and without polymer layer is successfully implemented at 200 degrees C under atmospheric pressure. Finite-element method (FEM) simulations on stress and deformation generated during bonding process are also presented in order to discuss their influence on bonding result of several pillar diameters and of concave sidewall angles originating from the manufacturing process. The alteration of parameters in FEM simulations would also be investigated to enhance the bonding outcome. The parameters include the diameter of pillar, the sidewall angle of concave, the shape of the concave opening, the addition of extra polymer layer under Cu concave layer, the bonding temperature, and the pitch of the pillar-concave structure. The implementation of Cu-Cu bonding using pillar-concave structure could have a prospective effect on existing packaging methods in semiconductor industry with benefits of applicability to various sorts of substrates and low bonding temperature.
Modeling and Characterization of TSV Capacitor and Stable Low-Capacitance Implementation for Wide-I/O Application
(2015-06-01)
Chang, Yao-Yen
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Ko, Cheng-Ta
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Yu, Tsung-Han
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Hsieh, Yu-Sheng
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Chen, Kuan-Neng
Equations of the electric field, surface charge, and silicon capacitance with respect to the surface potential of single through-silicon via (TSV) are derived by Poisson\'s equation. Four kinds of charges such as the electrons, holes, and ionized donor/acceptor charges in the p-type silicon substrate are brought into the equations. The numerical results of the surface charge show identical plots to planar MOS capacitor when the TSV radius is larger than 1 mu m. After presenting the fundamental C-V characteristics of one TSV capacitor, a simple design for gaining a stable low TSV capacitance value within a wide operating window (vertical bar V-ow vertical bar = 20 V) is proposed. Cu TSVs in this design are then demonstrated in the scheme of the wafer-level Cu/Sn to BCB hybrid bonding. The design gives the rational power consumption and delay, and the guideline for physical IC design is described in this paper. Without the oxide-trapped charge Q(ot) engineering in TSV oxide liner, neither considerations of the V-FB shifts nor the doping-type selection in silicon substrate, the design facilitates IC engineers to plan the high-speed TSVs at a specific location and to save the cost from TSV engineering simultaneously.
Non-Planarization Cu-Cu Direct Bonding and Gang Bonding with Low Temperature and Short Duration in Ambient Atmosphere
(2019-01-01)
Chou, Tzu-Chieh
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Yang, Kai-Ming
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Li, Jian-Chen
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Yu, Ting-Yang
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Chung, Ying-Ting
Low temperature (150 degrees C) and short duration Cu-Cu direct bonding, without planarization, and gang bonding approaches are demonstrated with excellent bond strength, electrical characteristics, and reliability. The concept is based on the high stress-led inducing deformation and internal friction to achieve low temperature bonding. In addition, the bonding structure has the advantage of high roughness tolerance on surface without CMP requirement. Compared to current products using Cu-Cu direct bonding at 350-400 degrees C with long duration and vacuum requirement, the breakthrough of proposed schemes provides the feasibility for product realization in 3D integration packaging.
Optimization of laser release process for throughput enhancement of fan-out wafer-level packaging
(2018-01-01)
Lee, Chia-Hsin
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Su, Jay
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Liu, Xiao
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Wu, Qi
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Lin, Jim-Wein
Fan-out wafer-level-packaging (FOWLP) technology has been developed with various advantages, such as smaller form factor, lower cost, and simplified supply chain for heterogeneous integration. There have been several process schemes like chip-first or chip-last FOWLP integration discussed widely in conferences in recent years. One process in all of these process schemes has in common is the use of a temporary carrier for subsequent redistribution layer (RDL) formation, chip stacking and molding processes. Although the separation of a temporary carrier from the reconstituted wafer could be achieved without significant hurdles, there were few studies addressing optimization of carrier separation for throughput enhancement. Thus, this paper is designed to address the needs in optimizing carrier separation process based upon laser ablation technology. Two phases of experiments were designed to select the appropriate laser release layer and define optimal laser settings. The first experiment was used to evaluate correlation of the laser absorption, laser energy, and spot pitch versus completeness of laser ablation. The second experiment included RDL-first FOWLP integration. At first, 300-mm glass carriers (1000 mu m thick) with coefficient of thermal expansion of 8 ppm/degrees C were treated by selected laser release layers. After deposition of 0.05-mu m Ti/0.15 mu m Cu on the glass carrier, passivation of around 8 mu m was coated and patterned by lithography for electroplating Cu interconnections with a density of approximately 10% of the surface area. Subsequently, die bonding, build-up layers, or molding compound were applied on top to form a 200-mu m reconstituted wafer. The reconstituted wafer was then separated from the glass carrier through a laser ablation process using a 355-nm laser to determine optimal throughput. Experiments to study correlation of laser release layer with laser settings along with a demonstration of full RDL-first FOWLP integration are discussed thoroughly to address the need of throughput enhancement, which could serve as cornerstone for realizing cost-effective RDL-first FOWLP.
Reliability of key technologies in 3D integration
(2013-01-01)
Ko, Cheng-Ta
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Chen, Kuan-Neng
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
3D IC packaging offers miniaturization, high performance, low power dissipation, high density and heterogeneous integration. Through-silicon via (TSV) and bonding technologies are the key technologies of 3D IC, and the corresponding reliability has to be well evaluated and qualified before real production applications. This paper reviews the emerging 3D interconnection technologies in worldwide 3D integration platforms with the latest reliability assessment results, including the reliability demonstration of Cu and oxide hybrid bonding in Ziptronix's platform, micro-bump and adhesive hybrid bonding in ITRI's platform, adhesive bonding followed by TSV formation in WOW alliance's platform, wide I/O interface TSV interposer in Xilinx's platform, and the active and passive TSV interposer in Samsung, TSMC and ASE's platforms. With low temperature bonding and TSV processes, optimized design and material selection to lower the induced stress and warpage, these platforms are successfully developed with enhanced reliability. The reliability of key technologies in 3D integration with these representative platforms are summarized in the paper to address the feasibility of 3D IC in mass production, which could be the guidelines for future development and applications of 3D integration technology. (C) 2012 Elsevier Ltd. All rights reserved.
Sealing Bump With Bottom-Up Cu TSV Plating Fabrication in 3-D Integration Scheme
(2013-05-01)
Chiang, Cheng-Hao
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Kuo, Li-Min
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Hu, Yu-Chen
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Huang, Wen-Chun
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Ko, Cheng-Ta
A sealing bump approach for the simplification of the conventional bottom-up copper through-silicon via (TSV) plating process flow is developed to reduce the process steps and increase the throughput without sacrificing the structure integrity and electrical performance. In this approach, TSV and bump formation can be achieved simultaneously through the bottom-up plating. Results from the analysis reveal excellent electrical characteristics and quality examination, which indicate that the proposed approach may be a good candidate for the TSV fabrication in 3-D integration.
Simulation Analysis of Structure Design for Low Temperature Cu-Cu Direct Bonding in Heterogeneous Integration and Advanced Packaging Systems
(2018-01-01)
Pan, Yu-Ming
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Yang, Yu-Tao
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Chou, Tzu-Chieh
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Yu, Ting-Yang
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Yang, Kai-Ming
In order to realize Cu-Cu bonding at low temperature, Cu pillar-concave structures on silicon substrate and on silicon substrate with another polymer layer, polyimide (PI), are both investigated through simulation. Height of Cu pillar, thickness of upper and lower silicon substrate, and thickness of Cu concave are simulated in this paper. The proposed structure could have great impacts on current semiconductor packaging technology, such as improvement of joint strength, enhancement of adhesive strength between various substrates, a Cu-Cu bonding process lower than 200 degrees C with simplified manufacturing process.
Study on Low Temperature Cu Bonding and Temporary Bond/De-Bond for RDL-First Fan-Out Panel Level Package
(2017-01-01)
Ko, Cheng-Ta
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Yang, Kai-Ming
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Lin, Jim-Wein
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Wang, Chih-Lun
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Chou, Tzu-Chieh
In this study, Cu-Cu bonding with pillar-concave structure on a polymer layer was investigated to realize better bonding quality at lower temperature, while a low-stress release layer for temporary bond and de-bond by laser ablation was demonstrated to handle a glass panel for re-distribution layer (RDL) process. The low temperature technology can be potentially applied for RDL-first fan-out panel level package (FOPLP).