Browsing by Author "Ko, Chun-Lin"

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A 2.4 to 5.4 GHz low power CMOS reconfigurable LNA for multistandard wireless receiver
(2007)
Fu, Chang-Tsung
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Ko, Chun-Lin
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Kuo, Chien-Nan
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交大名義發表
;
National Chiao Tung University
A CMOS reconfigurable LNA is reported. By combination of switched inductors and varactors it performs continuous frequency tuning from 2.4 to 5.4 GHz with 500MHz 3dB-bandwidth. Switching transistor is used to provide variable gain control over a 12dB-range. The LNA supports standards including Bluetooth, WiMAX, UWB mode-1, 802.11b/g and part of 802.11a. Fabricated in 0.13um CMOS process the LNA achieves up to 25dB power gain, 2.2dB noise figure, -1dBm IIP3 while consuming less than 5mV from 1-V power supply.
A 2.4-5.4-GHz Wide Tuning-Range CMOS Reconfigurable Low-Noise Amplifier
(2008-12-01)
Fu, Chang-Tsung
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Ko, Chun-Lin
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Kuo, Chien-Nan
;
Juang, Ying-Zong
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電子工程學系及電子研究所
A 2.4-5.4-GHz CMOS reconfigurable low-noise amplifier (LNA) is designed. It consists of two stages: a broadband input stage for a steady input matching and noise performance, and a reconfigurable band-selective stage which provides a wide-range frequency tuning from 2.4 to 5.4 GHz and a 12-dB stepped gain with linearity adjustment. The frequency tuning is conducted by a multitapped switching inductor and varactors. Careful design of the switching inductor achieves consistent performance among frequency configurations. The stepped gain and linearity adjustment are provided by a size-switchable transistor with a variable biasing. Fabricated in 0.13 mu m CMOS technology this LNA exhibits performance including up to 25 dB power gain, 2.2-3.1 dB noise figure and less than 5 mW power consumption under 1 V power supply.
A 210-GHz Amplifier in 40-nm Digital CMOS Technology
(2013-06-01)
Ko, Chun-Lin
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Li, Chun-Hsing
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Kuo, Chien-Nan
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Kuo, Ming-Ching
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Chang, Da-Chiang
This paper presents a 210-GHz amplifier design in 40-nm digital bulk CMOS technology. The theoretical maximum voltage gain that an amplifier can achieve and the loss of a matching network are derived for the optimization of a few hundred gigahertz amplifiers. Accordingly, the bias and size of transistors, circuit topology, and inter-stage coupling method can be determined methodically to maximize the amplifier gain. The measured results show that the amplifier exhibits a peak power gain of 10.5 dB at 213.5 GHz and an estimated 3-dB bandwidth of 13 GHz. The power consumption is only 42.3 mW under a 0.8-V supply. To the best of the authors' knowledge, this work demonstrates the CMOS amplifier with highest operation frequency reported thus far.
A 340 GHz Triple-Push Oscillator With Differential Output in 40 nm CMOS
(2014-12-01)
Li, Chun-Hsing
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Ko, Chun-Lin
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Kuo, Chien-Nan
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Kuo, Ming-Ching
;
Chang, Da-Chiang
A low-power triple-push oscillator with differential output is proposed in this letter. By extracting signals from the same current loop, the oscillator can naturally provide differential output without any additional active circuit or passive balun required. Therefore, the output power can be increased and the chip area and power consumption can be reduced. Realized in 40 nm CMOS technology, the proposed oscillator can oscillate at 340.6 GHz while providing equivalent isotropically radiated power (EIRP) as -21.8 dBm. The power consumption is only 34.1 mW from a 0.9 V supply. The oscillator core only occupies area of 0.028 mm(2).
A 37.5-mW 8-dBm-EIRP 15.5 degrees-HPBW 338-GHz Terahertz Transmitter Using SoP Heterogeneous System Integration
(2015-02-01)
Li, Chun-Hsing
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Chao, Tzu-Yuan
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Lai, Chih-Wei
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Chen, Wei-Cheng
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Ko, Chun-Lin
A low-cost terahertz transmitter is proposed by using system-on-package (SoP) heterogeneous system integration. A signal source in 40-nm CMOS is integrated with an antenna array on a Benzocyclobutene carrier through a broadband low-loss terahertz interconnect. The signal source adopting triple-push oscillator topology is able to produce a differential output without any additional balun circuit. Hence, the power consumption and the chip area can be reduced. The antenna array containing 50 patch antennas is differentially excited to give simulated directivity, efficiency, and antenna gain as high as 22.6 dB, 88%, and 22 dBi, respectively, at 335 GHz. The terahertz interconnect employs a resonator coupling technique to provide low-loss and broadband performance while occupying a small area. Measured results show that the proposed terahertz transmitter can work at 338.4 GHz with equivalent isotropically radiated power (EIRP) of 8.0 dBm while consuming only 37.5 mW from a 1-V supply. The measured half-power beam-width can be as narrow as 15.5 degrees. The EIRP can be further raised to 9.5 dBm as the supply V-DD is increased to 1.3 V. The CMOS chip only occupies an area as small as 0.028 mm(2). All of the design efforts enable the proposed terahertz transmitter to feature in small form factor, low power dissipation, low cost, and high performance. To the best of the authors\' knowledge, this is the most compact, lowest power, lowest cost, and high-performance SoP-based terahertz transmitter reported thus far.
A 8-mW 77-GHz Band CMOS LNA by Using Reduced Simultaneous Noise and Impedance Matching Technique
(2015)
Ko, Chun-Lin
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Li, Chun-Hsing
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Kuo, Chien-Nan
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Kuo, Ming-Ching
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Chang, Da-Chiang
This paper presents analysis and design of source inductance for multistage LNA at 77-GHz band in 90 nm CMOS technology. Instead of simultaneous noise and impedance matching, the analysis shows the optimum degeneration of the single stage design for millimeter-wave frequencies. A low-power 77-GHz band LNA has been demonstrated to verify the optimization result. By using the proposed method, the LNA exhibited a low noise figure of 5.1 dB and a gain of 18.1 dB at 78.5 GHz with only 8 mW from a 1-V power supply.
A Low-Cost Broadband Bondwire Interconnect for Heterogeneous System Integration
(2013)
Li, Chun-Hsing
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Ko, Chun-Lin
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Kuo, Chien-Nan
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Kuo, Ming-Ching
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Chang, Da-Chiang
A low-cost broadband interconnect, composed of bondwires and transmission lines, is proposed for heterogeneous system integration. By designing the length and the characteristic impedance of the transmission lines, the bondwire effect can be reduced to provide an interconnect with good return loss and low insertion loss. In this work, the chip and the carrier are realized in 90-nm CMOS and GIPD process, respectively. Measured results show that the return loss and the insertion loss are better than 10 dB and 1.1 dB, respectively, from DC to 45.2 GHz.
A Low-Cost DC-to-84-GHz Broadband Bondwire Interconnect for SoP Heterogeneous System Integration
(2013-12-01)
Li, Chun-Hsing
;
Ko, Chun-Lin
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Kuo, Chien-Nan
;
Kuo, Ming-Ching
;
Chang, Da-Chiang
A low-cost broadband bondwire interconnect is proposed for heterogeneous system integration. Transmission lines are incorporated with bondwires to form a two-path structure, which can effectively reduce the bondwire effect. Theoretical analysis is provided using a graphical method and it shows that the interconnect can give widest operation bandwidth from dc up to a maximum frequency f(max) if the length of the transmission lines is designed at an optimal electrical length theta(max) . In particular, theta(max) only depends on the characteristic impedance of the transmission lines. The achievable f(max) is limited by the bondwire inductance, i.e., smaller bondwire inductance is preferred to have wider operation bandwidth. An interconnect from a 0.18-mu m CMOS chip to a glass-integrated-passive-device carrier is designed to verify the proposed concept. Measured results show that the insertion loss and the return loss can be better than 3.0 and 13.4 dB, respectively, from dc to 84 GHz. The proposed interconnect shows around 3.2 times bandwidth of a single bondwire alone. To the best of authors' knowledge, this work demonstrates the bondwire interconnect with the widest operation bandwidth for heterogeneous system integration by using system-on-package reported thus far.
An Integrated CMOS Front-End Receiver with a Frequency Tripler for V-Band Applications
(2010-06-01)
Chen, Po-Hung
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Chen, Min-Chiao
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Ko, Chun-Lin
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Wu, Chung-Yu
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電子工程學系及電子研究所
A direct-conversion receiver integrated with the CMOS subharmonic frequency tripler (SET) for V-band applications is designed, fabricated and measured using 0.13-mu m CMOS technology. The receiver consists of a low-noise amplifier, a down-conversion mixer, an output buffer, and an SET. A fully differential SFT is introduced to relax the requirements on the design of the frequency synthesizer. Thus, the operational frequency of the frequency synthesizer in the proposed receiver is only 20 GHz. The fabricated receiver has a maximum conversion gain of 19.4 dB, a minimum single-side band noise figure of 10.2 dB, the input-referred 1-dB compression point of -20 dBm and the input third order inter-modulation intercept point of -8.3 dB. It draws only 15.8 mA from a 1.2-V power supply with a total chip area of 0.794 mm x 0.794 mm. As a result, it is feasible to apply the proposed receiver in low-power wireless transceiver in the V-band applications.
On-chip transmission line Modeling and applications to millimeter-wave circuit design in 0.13um CMOS technology
(2007)
Ko, Chun-Lin
;
Kuo, Chien-Nan
;
Juang, Ying-Zong
;
交大名義發表
;
National Chiao Tung University
This paper presents the on-chip transmission line modeling and applications to circuit design at millimeterwave (mm-wave) frequencies. The microstrip model of circuit simulators benefits in fast calculations of the characteristics of microstrip lines. As the structure of on-chip microstrip differs from the modeled structure, two key parameters of the microstrip model need to be modified for the different electromagnetic (EM) behavior according to the measured microstrip line. With proper parameters, the traditional transmission line model is able to accurately predict the real characteristic of on-chip microstrip lines without timeconsuming EM simulation. A mm-wave microstrip line filter and a single-stage cascode low noise amplifier (LNA) are fabricated to verify the model. All passive components for input/output matching networks and bias networks are onchip. The LNA takes the supply voltage and dc current of 1.4 V and 10 mA, respectively. A gain of 3.8dB and an input/output return loss of 8.5/7.OdB are measured at 60.3GHz. The simulation results in both circuits are in good agreement with measured data.