Browsing by Author "Ko, J"

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Investigation of DC hot-carrier degradation at elevated temperatures for n-channel metal-oxide-semiconductor field-effect-transistor of 0.13 mu m technology
(2006-04-01)
Lin, JC
;
Chen, SY
;
Chen, HW
;
Jhou, ZW
;
Lin, HC
In this study, n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) having 20 and 32 angstrom gate oxide thicknesses of 0.13 mu m technology were used to investigate DC hot-carrier reliability at elevated temperatures up to 125 degrees C. The research also focused on the degradation of analog properties after hot-carrier injection. On the basis of the results of experiments, the hot-carrier degradation of I-d.op (drain current defined on the basis of analog applications) is found to be the worst case among those of three types of drain current from room temperature to 125 degrees C. This result should provide valuable insight to analog circuit designers. As to the reverse temperature effect, the substrate current (I-b) commonly accepted as the parameter for,monitoring the drain-avalanche-hot-carrier (DAHC) effect should be modified since the drain current (I-d) degradation and I-b variations versus temperature have different trends. For the devices having a gate oxide thinner than 20 angstrom, we suggest that the worst condition in considering hot-carrier reliability should be placed at elevated temperatures.
Mismatches after hot-carrier injection in advanced complementary metal-oxide-semiconductor technology particularly for analog applications
(2006-04-01)
Chen, SY
;
Lin, JC
;
Chen, HW
;
Lin, HC
;
Jhou, ZW
In this paper, the impact of hot carrier stress on the mismatch properties of n and p metal-oxide-semiconductor (MOS) field-effect transistors (FETs) with different sizes produced using 0.15 mu m complementary MOS (CMOS) technology is presented for the first time. The research reveals that hot-carrier injection (HCI) does degrade the matching properties of MOSFETs. The degree of degradation closely depends on the strength of the HC effect. Thus, it is found that, under the stress condition of drain avalanche hot carrier (DAHC), the properties of nMOSFETs rapidly and greatly become worse, but the changes are small for pMOSFETs. For analog circuit parameters, it is found that the after-stress lines of n and pMOSFETs exhibit a cross point in sigma (Delta V-t,V-op) drawings. It is suggested that the cross point can be used to indicate the minimal size in order for n and p pairs to have the same degree of Delta V-t.op mismatch in designing analog circuits. In addition, interpretations for the differences between n and pMOSFETs and between Delta V-t,V-op and I-ds,I-op mismatches are provided with experimental verifications.