Browsing by Author "Kowalski, Jeff M."

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3D 65nm CMOS with 320 degrees C Microwave Dopant Activation
(2009)
Lee, Yao-Jen
;
Lu, Yu-Lun
;
Hsueh, Fu-Kuo
;
Huang, Kuo-Chin
;
Wan, Chia-Chen
For the first time, CMOS TFTs of 65nm channel length have been demonstrated by using a novel microwave dopant activation technique. A low temperature microwave anneal is. demonstrated and discussed in this study. We have successfully activated the poly-Si gate electrode and source/drain junctions, BF2 for p-MOS TFTs and P-31 for n-MOS TFTs at a low temperature of 320 degrees C without diffusion. The technology is promising for high performance and low cost upper layer nanometer-scale transistors as required by low temperature 3D-ICs fabrication.
Nanoscale p-MOS Thin-Film Transistor With TiN Gate Electrode Fabricated by Low-Temperature Microwave Dopant Activation
(2010-05-01)
Lu, Yu-Lun
;
Hsueh, Fu-Kuo
;
Huang, Kuo-Ching
;
Cheng, Tz-Yen
;
Kowalski, Jeff M.
In this letter, nanoscale p-MOS TFTs with a TiN gate electrode were realized using a novel microwave (MW) dopant-activation technique. We compared both low-temperature MW annealing and rapid thermal annealing. We successfully activated the source/drain region and suppressed the short-channel effects using low-temperature MW annealing. This technique is promising from the viewpoint of realizing high-performance and low-cost upper layer nanoscale transistors required for low-temperature 3-D integrated circuit fabrication.