Browsing by Author "Ku, Chun-Wei"

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A 1280x720 pixels 30Frames/s H.264/MPEG-4 AVC intra encoder
(2006)
Cheng, Chao-Chung
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Ku, Chun-Wei
;
Chang, Tian-Sheuan
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents an HDTV size H.264/MPEG-4 AVC intra encoder suitable for DSC and digital video camera applications. The chip reduces the gate count by saving the costly plane mode and enhances the video quality with the improved cost function. With careful scheduling and high performance function unit, the developed chip can easily support 29.46M pixels/s still image encoding and real-time moving picture intra coding of HDTV 720p@30fps video application when clocked at 117.28MHz under 0.18um CMOS process.
A 61 MHz 72K gates 1280x720 30FPS H.264 intra encoder
(2007)
Li, De-Wei
;
Ku, Chun-Wei
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Cheng, Chao-Chung
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Lin, Yu-Kun
;
Chang, Tian-Sheuan
This paper presents an HD720p 30 frames per see H.264 intra encoder operated at 61MHz with just 72K gate count. We achieve the low cost and low operating frequency with the highly utilized variable pixel scheduling, and a modified three-step fast algorithm. Thus, the resulted design only needs half of operating frequency and reduces 30% of area cost compared to the previous HD720p intra encoder design.
A high-definition H.264/AVC intra-frame codec IP for digital video and still camera applications
(2006-08-01)
Ku, Chun-Wei
;
Cheng, Chao-Chung
;
Yu, Guo-Shiuan
;
Tsai, Min-Chi
;
Chang, Tian-Sheuan
This paper presents a real-time high-definition 720p@30fps H.264/MPEG-4 AVC intra-frame codec IP suitable for digital video and digital still camera applications. The whole design is optimized in both the algorithm and architecture levels. In the algorithm level, we propose to remove the area-costly plane mode, and enhance the cost function to reduce hardware cost and to increase the processing speed while provide nearly the same quality. In the architecture design, in additional to the fast module implementation the process is arranged in the macroblock-level pipelining style together with three careful scheduling techniques to avoid the idle cycles and improve the data throughput. The whole codec design only needs 103 K gate count for a core size of 1.28 x 1.28 mm(2) and achieves real-time encoding and decoding at 117 and 25.5 MHz, respectively, when implemented by 0.18-mu m CMOS technology.