Browsing by Author "Ku, J"

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A novel erase scheme to suppress overerasure in a scaled 2-bit nitride storage flash memory cell
(2004-09-01)
Yeh, CC
;
Wang, TH
;
Tsai, WJ
;
Lu, TC
;
Liao, YY
The cause of over-erasure in a two-bit nitride storage Flash memory cell is investigated. Extra positive charges accumulated above the n(+) unction and channel-shortening enhanced drain-induced barrier lowering effect are found to be responsible for threshold voltage (V-t) lowering in an over-erased cell. A modified erase scheme is proposed to resolve this issue. By applying a source voltage during erase, the erase speed can be well controlled for cells with different channel lengths and a wide range of program-state Vt distribution, which will reduce overerasure significantly.
Investigation of programmed charge lateral spread in a two-bit storage nitride flash memory cell by using a charge pumping technique
(2004)
Gu, SH
;
Wang, MT
;
Chan, CT
;
Zous, NK
;
Yeh, CC
The lateral distribution of programmed charge in a hot electron program/hot hole erase nitride storage flash cell is investigated by using a charge pumping technique. Our study shows that the secondly programmed bit has a wider trapped charge distribution than the first programmed bit. In addition, we find prograrnmed charge spreads further into the channel with program/erase cycle number.
Lateral migration of trapped holes in a nitride storage flash memory cell and its qualification methodology
(2004-09-01)
Zous, NK
;
Lee, MY
;
Tsai, WJ
;
Kuo, A
;
Huang, LT
The negative threshold voltage (V-t) shift of a nitride storage flash memory cell in the erase state will result in an increase in leakage current. By utilizing a charge pumping method, we found that trapped hole lateral migration is responsible for this V-t shift. Hole transport in nitride is characterized by monitoring gate induced drain leakage current and using a thermionic emission model. The hole emission induced V-t shift shows a linear correlation with bake time in a semi-logarithm plot and its slope depends on the bake temperature. Based on the result, an accelerated qualification method for the negative V-t drift is proposed.
Temperature effect on read current in a two-bit nitride-based trapping storage flash EEPROM cell
(2004-07-01)
Liu, MY
;
Chang, YW
;
Zous, NK
;
Yang, I
;
Lu, TC
The temperature effect on the read current of a two-bit nitride-storage Flash memory cell is investigated. In contrast to a conventional silicon-oxide-nitride-oxide (SONOS) cell with uniform Fowler-Nordheim (FN) programming, a significant high-V-T state read current increase, which results in the read window narrowing at high temperature, is observed in a channel hot electron (CHE) programmed cell. The increment of high-V-T state leakage current shows a positive correlation with program/erase threshold voltage window. Since the temperature effect is very sensitive to a locally trapped charge profile, a two-dimensional simulation with a step charge profile is employed to characterize the relationship between current increment and both charge width and charge density.