Browsing by Author "Ku, Po-Yi"

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Nitride Induced Stress Affecting Crystallinity of Sidewall Damascene Gate-All-Around Nanowire Poly-Si FETs
(2020-01-01)
Shen, Chuan-Hui
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Chen, Wei-Yen
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Lee, Shen-Yang
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Ku, Po-Yi
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Chao, Tien-Sheng
In this article, poly-Si gate-all-around (GAA) field effect transistors (FETs) using sidewall damascene method are successfully demonstrated. By manipulating the stress which is imposed by nitride layer, the crystallinity of poly-Si channels can be modified easily by changing the thickness of nitride layer. The better crystallinity of the devices with 60 & x00A0;nm top nitride is attributed to larger average grain size and fewer defects, leading to higher field-effect carrier mobility compared to 40 and 80 & x00A0;nm top nitride layer devices. Both n-type and p-type devices exhibit superior electrical characteristics including higher on-state current of 40 & x00A0;& x03BC;A & x002F;& x03BC;m (n-type) and 26 & x00A0;& x03BC;A & x002F;& x03BC;m (p-type), steep subthreshold swing of 82 & x00A0;mV & x002F;dec. (n-type) and 104 & x00A0;mV & x002F;dec. (p-type), an extremely low drain-induced barrier lowering (DIBL) of 4.6 & x00A0;mV & x002F;V (n-type) and 16.6 & x00A0;mV & x002F;V (p-type), and high I_on& x002F;I_off current ratio larger than seven orders of magnitude. The thermal stability and gate stress reliability measurement of sidewall damascene GAA nanowire poly-Si devices were also investigated. With better crystallinity, electrical characteristics of GAA nanowire poly-Si devices degrade less under same elevated temperature condition. Devices characteristics remain unchanged after long gate stress time. This simple fabrication process makes it a potential candidate for future three-dimensional integrated-circuit (3D-IC) and low-cost Internet of Things (IoTs) applications.