Browsing by Author "Ku, S. H."

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Analysis and Realization of TLC or even QLC Operation with a High Performance Multi-times Verify Scheme in 3D NAND Flash memory
(2018-01-01)
Lu, C. C.
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Cheng, C. C.
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Chiu, H. P.
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Lin, W. L.
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Chen, T. W.
Feasibility of multi-times verify (MTV) scheme on triple-level cell (TLC) and quad-level cell (QLC) operations of charge-trap storage 3D NAND memories is investigated comprehensively. Results reveal that random telegraph noise (RTN) and program noise are the major factors affecting lower (LB) and upper boundaries (HB) of Vt distribution, respectively. Enlargement of operation window and reduction of ECC usage with MTV scheme to mitigate RTN-induced LB tail are demonstrated on TLC and QLC operations. In addition, the impact of program noise on HB Vt under various process conditions and ISPP steps is studied experimentally and also explained by our Monte Carlo simulator. Finally, program performance and reserved margin with and without MTV scheme applied on TLC and QLC operation are demonstrated.
Chip-Level Characterization and RTN-Induced Error Mitigation beyond 20nm Floating Gate Flash Memory
(2018-01-01)
Lin, T. W.
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Ku, S. H.
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Cheng, C. H.
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Lee, C. W.
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Ijen-Huang
Vt instability caused by random telegraph noise (RTN) in floating gate flash memories beyond 20nm is studied comprehensively. Experiments reveal that the RTN would cause Vt distribution with a kinked tail which re-distributes to a "Gaussian-like" shape rapidly and was measured by the self established Budget Product Tester (BPT). A Multi-Times Verify (MTV) algorithm to mitigate the statistical tail, thus enlarging operation window is also exhibited by BPT. In further, a probability model to portray the compact Vt distribution under MTV is proposed. Finally, the impact of MTV on lowering the requirement of Error-correcting code (ECC) bit is also demonstrated.
Error Characterization and ECC Usage Relaxation beyond 20nm Floating Gate NAND Flash Memory
(2018-01-01)
Ku, S. H.
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Lin, T. W.
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Cheng, C. H.
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Lee, C. W.
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Chen, Ti-Wen
Endurance of floating gate flash memories at 19nm node and beyond is studied comprehensively. Experiments reveal that the random telegraph noise (RTN) would degrade the read margin with a tail, which quickly reshapes into a symmetric Gaussian form in a lightly-stressed state. After heavy stress, the lower part of tail would spread further while the upper part keeps roughly overlapped with that during fresh. This unique behavior, which was firstly measured by the self-established Budget Product Tester (BPT), can be explained by stress-induced hole trap creation. To investigate the impact of RTN on operation window, a novel algorithm of Multi-Times-Verify accompanied with the optimal Read-Retry (MTVR2) is proposed and validated by BPT. The advantage of MTVR2 to reduce the requirement of Error-Correcting Code (ECC) bit is demonstrated. Finally, the improvement of bit error rate (BER) in TLC operation with MTVR(2 )is also evaluated.
Grain Boundary Trap-Induced Current Transient in a 3-D NAND Flash Cell String
(2019-04-01)
Lin, Wei-Liang
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Tsai, Wen-Jer
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Cheng, C. C.
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Ku, S. H.
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Liu, Lenvis
Transient cell current caused by the trapping/detrapping of grain boundary traps in the polycrystalline silicon (poly-Si) channel of a 3-D NAND cell string is comprehensively studied in this paper. This transient has a time constant of 10 mu s or longer and is strongly dependent on the bias history. It is also affected by the trap distribution as revealed by TCAD simulations. Sensing offset between program verify and read results in "pseudo" charge loss/gain that reduces the sensing margin. The posttreatment of the poly-Si channel is suggested to mitigate this effect.
Hot-Carrier Injection-Induced Disturb and Improvement Methods in 3D NAND Flash Memory
(2019-01-01)
Lin, Wei-Liang
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Tsai, Wen-Jer
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Cheng, C. C.
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Lu, Chun-Chang
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Ku, S. H.
We investigate a hot-carrier injection- induced program disturb in a 3D NAND flash memory. As there exist specific coding patterns, a "down-coupling" region and a "pre-charge" regions are formed during program-verify and the following program phases, respectively, in the inhibit cell strings. A high heating field is built nearby the PGM wordline. Hot carriers may inject into the inhibit cells as Vpgm is applied. Soft ramp-down and pre-turn-on schemes are proposed to mitigate this disturb.
Polycrystalline-Silicon Channel Trap Induced Transient Read Instability in a 3D NAND Flash Cell String
(2016-01-01)
Tsai, Wen-Jer
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Lin, W. L.
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Cheng, C. C.
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Ku, S. H.
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Chou, Y. L.
Vt instability caused by grain-boundary trap (GBT) in the poly-crystalline silicon (poly-Si) channel of a 3D NAND string are comprehensively studied. Experimental results reveal that trapping/detrapping of GBT would cause transient cell current with a time constant of lOus or longer, and this transient is strongly affected by the bias history. Sensing offset between program/erase verify (PV/EV) and read (RD) results in "pseudo" charge loss/gain that reduces the sensing margin. Modified EV, PV, or RD bias schemes are suggested to mitigate this effect.
Program Charge Effect on Random Telegraph Noise Amplitude and Its Device Structural Dependence in SONOS Flash Memory
(2009)
Chiu, J. P.
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Chou, Y. L.
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Ma, H. C.
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Wang, Tahui
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Ku, S. H.
Nitride program charge effects on random telegraph noise (RTN) in SONOS flash cells are investigated. We measure and simulate RTN amplitudes in floating gate flash, planar SONOS, and FinFET SONOS cells. We find that a planar SONOS has a wide spread in RTN amplitude after programming while a floating gate flash cell has identical RTN amplitude in erase and program states. The spread of program-state RTN amplitudes in a planar SONOS is attributed to a current-path percolation effect caused by random discrete nitride charges. The program-state RTN spread can be significantly reduced in FinFET SONOS.
Program Trapped-Charge Effect on Random Telegraph-Noise Amplitude in a Planar SONOS Flash Memory Cell
(2009-11-01)
Ma, H. C.
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Chou, Y. L.
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Chiu, J. P.
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Wang, Tahui
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Ku, S. H.
Program-charge effects in a SONOS Flash cell on the amplitude of random telegraph noise (RTN) are investigated. We measure RTN in 45 planar SONOS cells and 40 floating-gate (FG) cells in erase state and program state, respectively. We find that a SONOS cell has a wide spread in RTN amplitudes after programming, while an FG cell has identical RTN amplitudes in erase and program states at the same read-current level. A 3-D atomistic simulation is performed to calculate RTN amplitudes. Our result shows that the wide spread of program-state RTN amplitudes in a SONOS cell is attributed to a current-path-percolation effect caused by random discrete nitride charges.
Variations of V(t) Retention Loss in a SONOS Flash Memory Due to a Current-Path Percolation Effect
(2011-04-01)
Chou, Y. L.
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Chung, Y. T.
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Wang, Tahui
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Ku, S. H.
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Zou, N. K.
Discrete nitride program charge loss in a small-area SONOS Flash memory cell during retention is observed. Our measurement shows that a retention V(t) of a programmed SONOS cell exhibits a stepwise evolution with retention time. Individual single-program charge-loss-induced threshold voltage shifts (Delta V(t)) are characterized. We find the following: 1) The magnitude of Delta V(t) exhibits an exponential distribution, which is believed due to a current-path percolation effect caused by random program charges and substrate dopants, and 2) program-state V(t) retention loss has large variations in different cells and P/E cycles due to the percolation effect. We develop a Monte Carlo analysis to take into account the distribution of Delta V(t) and a tunneling front model to study the spread of a retention V(t) distribution in a SONOS Flash memory.
Variations of V-t Retention Loss in a SONOS Flash Memory Due to a Current-Path Percolation Effect
(2011-04-01)
Chou, Y. L.
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Chung, Y. T.
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Wang, Tahui
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Ku, S. H.
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Zou, N. K.
Discrete nitride program charge loss in a small-area SONOS Flash memory cell during retention is observed. Our measurement shows that a retention V-t of a programmed SONOS cell exhibits a stepwise evolution with retention time. Individual single-program charge-loss-induced threshold voltage shifts (Delta V-t) are characterized. We find the following: 1) The magnitude of Delta V-t exhibits an exponential distribution, which is believed due to a current-path percolation effect caused by random program charges and substrate dopants, and 2) program-state V-t retention loss has large variations in different cells and P/E cycles due to the percolation effect. We develop a Monte Carlo analysis to take into account the distribution of Delta V-t and a tunneling front model to study the spread of a retention V-t distribution in a SONOS Flash memory.