Browsing by Author "Kuan, Yen-Cheng"

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A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS
(2018-11-01)
Wang, X. Shawn
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Jin, Xin
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Du, Jieqiong
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Li, Yilei
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Du, Yuan
This brief presents a two-way time-interleaved twostep pipelined analog-to-digital converter (ADC) architecture built upon a new concept of virtual-ground sampling, featuring merged front-end track-and-hold, residue generation, input termination, and buffering. This architecture is investigated to alleviate the front-end performance tradeoff among the total-harmonic- distortion, bandwidth, and sampling rate (interleaving factor). A 2-GS/s 8b ADC using the new architecture was designed and fabricated in 28-nm CMOS, achieving 43-dB SNDR and 55-dB SFDR up to Nyquist frequency.
A Fully Integrated Wireless SoC for Motor Function Recovery After Spinal Cord Injury
(2017-06-01)
Lo, Yi-Kai
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Kuan, Yen-Cheng
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Culaclii, Stanislav
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Kim, Brian
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Wang, Po-Min
This paper presents a wirelessly powered, fully integrated system-on-a-chip (SoC) supporting 160-channel stimulation, 16-channel recording, and 48-channel bio-impedance characterization to enable partialmotor function recovery through epidural spinal cord electrical stimulation. A wireless transceiver is designed to support quasi full-duplex data telemetry at a data rate of 2 Mb/s. Furthermore, a unique in situ bio-impedance characterization scheme based on time-domain analysis is implemented to derive the Randles cell electrode model of the electrode-electrolyte interface. The SoC supports concurrent stimulation and recording while the high-density stimulator array meets an output compliance voltage of up to +/- 10 V with versatile stimulus programmability. The SoC consumes 18 mW and occupies a chip area of 5.7 mm x 4.4 mm using 0.18 mu m high-voltage CMOS process. In our in vivo rodent experiment, the SoC is used to perform wireless recording of EMG responses while stimulation is applied to enable the standing and stepping of a paralyzed rat. To facilitate the system integration, a novel thin film polymer packaging technique is developed to provide a heterogeneous integration of the SoC, coils, discrete components, and high-density flexible electrode array, resulting in a miniaturized prototype implant with a weight and form factor of 0.7 g and 0.5 cm(3), respectively.
A Millimeter Wave Digital CMOS Baseband Transceiver for Wireless LAN Applications
(2019-01-01)
Chiu, Kang-Lun
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Chan, Hsun-Wei
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Lee, Wei-Che
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Wu, Chang-Ting
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Lopez, Henry
In this paper, we introduce a 10 Gbps digital baseband transceiver with IV supply voltage, 16-QAM, 3/4 code rate single carrier mode using 28 nm CMOS process to do the implementation. In millimeter wave communications, well-defined standard, IEEE 802.11ad is referenced for our system design and simulation. We target at modified chip rate 2.5 GHz with 4 times parallelism hardware at clock rate 625 MHz. The overall transceiver architecture design with hardware implementation considerations will be proposed. With the smart shared memory allocation, we can reduce 31% of the total amount. According to the referenced specifications, we achieve the required bit error rate 3 x 10(-7) before SNR 18.5 dB. After the system algorithm design, we implement the hardware with the core area 2.92 mm(2) with measured power 1.8 Watt for baseband transceiver chip. The performance of energ,y per bit is 0.023 nJ and 0.211 nJ per hit 6w Tx and Rx, including ADC/DAC.
A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things
(2018-01-01)
Du, Li
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Du, Yuan
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Li, Yilei
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Su, Junjie
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Kuan, Yen-Cheng
Convolutional neural network (CNN) offers significant accuracy in image detection. To implement image detection using CNN in the Internet of Things (IoT) devices, a streaming hardware accelerator is proposed. The proposed accelerator optimizes the energy efficiency by avoiding unnecessary data movement. With unique filter decomposition technique, the accelerator can support arbitrary convolution window size. In addition, max-pooling function can be computed in parallel with convolution by using separate pooling unit, thus achieving throughput improvement. A prototype accelerator was implemented in TSMC 65-nm technology with a core size of 5 mm(2). The accelerator can support major CNNs and achieve 152GOPS peak throughput and 434GOPS/W energy efficiency at 350 mW, making it a promising hardware accelerator for intelligent IoT devices.
A Single Layer 3-D Touch Sensing System for Mobile Devices Application
(2018-02-01)
Du, Li
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Liu, Chun-Chen
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Zhang, Yan
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Li, Yilei
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Du, Yuan
Touch sensing has been widely implemented as a main methodology to bridge human and machine interactions. The traditional touch sensing range is 2-D and therefore limits the user experience. To overcome these limitations, we propose a novel 3-D contactless touch sensing called Airtouch system, which improves user experience by remotely detecting single/multi-finger position. A single layer touch panel with triangle-shaped electrodes is proposed to achieve multitouch detection capability as well as manufacturing cost reduction. Moreover, an oscillator-based-capacitive touch sensing circuit is implemented as the sensing hardware with the bootstrapping technique to eliminate the interchannel coupling effects. To further improve the system accuracy, a grouping algorithm is proposed to group the useful channels' data and filter out hardware noise impact. Finally, improved algorithms are proposed to eliminate the fringing capacitance effect and achieve accurate finger position estimation. EM simulation proved that the proposed algorithm reduced the maximum systematic error by 11 dB in the horizontal position detection. The proposed system consumes 2.3 mW and is fully compatible with existing mobile device environments. A prototype is built to demonstrate that the system can successfully detect finger movement in a vertical direction up to 6 cm and achieve a horizontal resolution up to 0.6 cm at 1 cm finger-height. As a new interface for human and machine interactions, this system offers great potential in finger movement detection and gesture recognition for small-sized electronics and advanced human interactive games for mobile device.
An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch
(2019-01-01)
Swindlehurst, Eric
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Jensen, Hunter
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Petrie, Alexander
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Song, Yixin
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Kuan, Yen-Cheng
An 8-bit 10-GHz 8x time-interleaved SAR ADC in 28-nm CMOS incorporates an aggressively scaled DAC with grouped capacitors in a symmetrical comb structure to afford a threefold reduction in the bottom-plate parasitic capacitance. A dual-path bootstrapped switch decouples critical signal from nonlinear capacitance to boost the sampling SFDR by more than 5 dB. The ADC demonstrates an SNDR of 36.9 dB at Nyquist while consuming 21 mW, yielding an FoM of 37 fJ/conv.-step, the lowest among the reported ADCs with similar speeds and resolutions and more than 2x improvement from the state-of-the-art.
An 8.8-GS/s 8b Time-Interleaved SAR ADC with 50-dB SFDR Using Complementary Dual-Loop-Assisted Buffers in 28nm CMOS
(2018-01-01)
Wang, X. Shawn
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Chan, Chi-Hang
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Du, Jieqiong
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Wong, Chien-Heng
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Li, Yilei
This paper presents an 8.8 GS/s 16-way time-interleaved asynchronous SAR ADC fabricated in 28-nm CMOS technology. A two-level 2x8 master-slave hierarchical interleaved architecture is employed. A complementary dual-loop-assisted buffer is proposed to achieve both high linearity and bandwidth with low power. This time-interleaved ADC achieves 38.4-dB SNDR and 50-dB SFDR with a Nyquist input at 8.8 GS/s sampling rate and consumes 83.4 mW, resulting in a 140 fJ/conv.-step Walden FOM with buffers.
Digital PLL for Phase Noise Cancellation in Ring Oscillator-Based I/Q Receivers
(2016)
Chen, Zuow-Zun
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Li, Yilei
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Kuan, Yen-Cheng
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Hu, Boyu
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Wong, Chien-Heng
A digital phase noise cancellation technique for ring oscillator-based I/Q receivers is presented. Ring oscillator phase noise, including supply-induced phase noise, is extracted from digital phase-locked loop (DPLL) and used to restore the randomly rotated baseband signal in digital domain. The receiver prototype fabricated in 65nm CMOS technology achieves phase noise reduction from - 88 to - 109dBc/Hz at 1MHz offset, and an integrated phase noise (IPN) reduction from - 16.8 to - 34.6dBc, when operating at 2.4GHz.
DPLL for Phase Noise Cancellation in Ring Oscillator-Based Quadrature Receivers
(2017-04-01)
Chen, Zuow-Zun
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Kuan, Yen-Cheng
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Li, Yilei
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Hu, Boyu
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Wong, Chien-Heng
In this paper, a low overhead phase noise cancellation technique for ring oscillator (RO)-based quadrature receivers is presented. The proposed technique operates in background and extracts RO phase noise as well as supply-induced phase noise from the digital phase-locked loop. The obtained phase noise information is then used to restore the randomly rotated baseband signal in digital domain. A receiver prototype is fabricated in standard 65-nm CMOS technology. It demonstrates a phase noise reduction from -88 to -109 dBc/Hz at 1-MHz offset and an integrated phase noise reduction from -16.8 to -34.6 dBc when operating at 2.4 GHz.
Millimeter-wave Field Experiments with Many Antenna Configurations for Indoor Multipath Environments
(2017-01-01)
Comiter, Marcus
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Crouse, Michael
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Kung, H. T.
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Tarng, Jenn-Hwan
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Tsai, Zuo-Min
Next-generation wireless networks, such as 5G networks, will use millimeter waves (mmWaves) operating at 28 GHz, 38 GHz, 60 GHz, or higher frequencies to deliver unprecedentedly high data rates, e.g., 10 gigabits per second. Due to high attenuation at this higher frequency, use of directional antennas is commonly suggested for mmWave communication. It is therefore important to study how different antenna configurations at the transmitter and receiver effect received power and data throughput. In this paper, we describe field experiments with mmWave antennas for indoor multipath environments and report measurement results on a multitude of antenna configurations. Specifically, we examine four different mmWave systems, operating at two different frequencies (38 and 60 GHz), using a number of different antennas (horn antennas, omnidirectional antennas, and phase arrays). For each system, we systematically collect performance measurements (e.g., received power), and use these to examine the effects of beam misalignment on signal quality, the presence of multipath effects, and susceptibility to blockage. We capture interesting phenomena, including a multipath scenario in which a single receiver antenna can receive two copies of signals transmitted from the same transmitter antenna over multiple paths. From these field experiments, we discuss lessons learned and draw several conclusions, and their applicability to the design of future mmWave networks.
Multi-Gbps Tri-Band 28/38/60-GHz CMOS Transmitter for Millimeter-Wave Radio System-on-Chip
(2019-01-01)
del Rio, David
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Yoon, Daekeun
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Chen, Fan-Ta
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Zhang, Yan
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Liang, Chia-Jen
This paper presents the design of a novel tri-band 28-nm CMOS transmitter for the 28, 38 and 60-GHz mm-wave bands. It consists of a 4-stage power amplifier preceded by a wideband active mixer. The PA employs wideband enhancing techniques and low-loss switches to achieve the tri-band operation, as well as a linearization loop to enhance the OP1dB by more than 3.5 dB. The PA exhibits a measured gain of 22/23/12 dB in the 3 bands and a Psat higher than 10 dBm. The transmitter CG is 10/15/4 dB and it is capable of transmitting a 1.5-Gbps modulated signal. The PA and the transmitter consume 430 and 431 mW of DC power and occupy 0.87 and 1.14 mm(2), respectively.