Browsing by Author "Kumar, Malkundi Puttaveerappa Vijay"

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Impacts of the Shell Doping Profile on the Electrical Characteristics of Junctionless FETs
(2015-11-01)
Kumar, Malkundi Puttaveerappa Vijay
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Hu, Chia-Ying
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Kao, Kuo-Hsing
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Lee, Yao-Jen
;
Chao, Tien-Sheng
This paper presents the impacts of an advanced shell doping profile (SDP) on the electrical characteristics of a junctionless (JL) FET in terms of OFF-current, subthreshold swing (SS), and ON-current by a numerical simulator. Due to the potential mirroring effect, a special observation stemming from the SDP, the carriers can enter the intrinsic region from the doped surface reducing the series resistance though the junction depth is smaller than 5 nm. The proposed doping profile provides an additional structure parameter for designing a JL FET showing the mitigated short-channel effects, a better SS, and a higher ON/OFF current ratio for sub-20-nm channel length. Compared with traditional devices, a JL FET with the proposed SDP shows a lower OFF-current by decades and less electrical characteristics variation caused by the nanowire diameter variation. The SDP not only reduces the series resistance of a JL FET but also poses a possible solution of avoiding the negative impacts of quantum confinement for advanced technology nodes.
Improving the Electrical Performance of a Quantum Well FET With a Shell Doping Profile by Heterojunction Optimization
(2017-09-01)
Kumar, Malkundi Puttaveerappa Vijay
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Hu, Chia-Ying
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Walke, Amey Mahadev
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Kao, Kuo-Hsing
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Chao, Tien-Sheng
This paper investigates the impacts of typical semiconductor material properties-electron affinity, bandgap, and dielectric constant, on the electrical performance of a p-type core-shell heterojunction nanowire FET by numerical simulations. At the heterojunction, a valence band offset of 200 meV forms a sufficient energy barrier confining the holes in the quantum well, resulting in the optimal OFF-state current. A higher dielectric constant of the shell region is found to be able to decrease the leakage current of the device. The optimum conditions from the parameter analysis are demonstrated by a realistic and achievable material combination of Si/SiGe for the core-shell configuration. This paper provides physical insights into the materialwise impacts for designing the proposed transistor showing the reduced OFF-current and a better subthreshold swing for low-power applications.
Junctionless FETs With a Fin Body for Multi-V-TH and Dynamic Threshold Operation
(2018-08-01)
Kumar, Malkundi Puttaveerappa Vijay
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Lin, Jer-Yi
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Kao, Kuo-Hsing
;
Chao, Tien-Sheng
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電子物理學系
In this paper, a n-type junctionless FET (JLFET) with a p-type fin body (FB) is investigated using a 3-D numerical simulator. We show that the proposed device (FB-JLFET) with a p+FB can control the electrostatic potential of the channel more efficiently for multi-V-TH (threshold voltage) and dynamic threshold (DT) operation. Moreover, body bias application is implemented in FB-JLFET and a large body factor (gamma) is predicted for wide range V-TH modulation. Thanks to the stronger potential coupling between the channel and FB, the proposeddevice exhibits gamma improvement compared to the conventional JL bulk FinFETs under the same electrostatic control. In addition, DT operation is studied in the form of a JLFET for the first time and it exhibits 37% improvement of the on-state drive current and better subthreshold swing (S.S.) compared to FB-JLFET without DT. This paper provides the feasibility of multi-V-TH operation with body bias mode for high performance or low-power applications and DT operation for high-speed circuits with low power consumption.
Junctionless Nanosheet (3 nm) Poly-Si TFT: Electrical Characteristics and Superior Positive Gate Bias Stress Reliability
(2018-01-01)
Lin, Jer-Yi
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Kumar, Malkundi Puttaveerappa Vijay
;
Chao, Tien-Sheng
;
電子物理學系
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Department of Electrophysics
In this letter, a junctionless (JL) poly-Si thin-film transistor (TFT) with a 3-nm-thick nanosheet channel is successfully fabricated using the low-temperature atomic level etching process. An inversion-mode (IM) TFT is also prepared for performance comparison and reliability investigation of positive gate bias stress (PGBS). In comparison with the IM-TFT, the JL-TFT exhibits superior PGBS reliability. The origin of the difference in degradation rates between the JL and IM-TFTs is ascribed to the different transport mechanisms and different gate dielectric fields under the same gate over-drivestress. Nanosheet JL-TFTs with a 3-nm channel thickness show excellent S.S (69 mV/decade) and extremely low off-current (1.93 fA). Results indicate that it is a promising candidate for low-power 3-D integrated circuits.
Variable-Channel Junctionless Poly-Si FETs: Demonstration and Investigation With Different Body Doping Concentrations
(2018-09-01)
Lin, Jer-Yi
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Tsai, Chan-Yi
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Shen, Chiuan-Huei
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Chung, Chun-Chih
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Kumar, Malkundi Puttaveerappa Vijay
In this letter, tri-gate polycrystalline silicon variable-channel junctionless transistors (VC-JLTs), which consist of a counter-doped p-type body below an n(+) active device layer, are successfully demonstrated to show a better performance compared with conventional tri-gate nanosheet (NS) JLTs. Because the potential barrier between the n-channel and p-body in the VC-JLT can be controlled by the gate, the effective conduction channel behaves as a "variable" channel, in which the conduction thickness is thinner or thicker than the physical n(+) thickness for the OFF or ON state, respectively. Consequently, the VC-JLT can turn OFF more efficiently due to the enhanced volume depletion and turn ON with a smaller series resistance owing to the augmented conduction volume. In addition, for the first time, the impact of the body doping concentration is investigated and the performance sensitivities of VC-JLTs in terms of I-ON, V-T, S.S., and DIBL are discussed with respect to the dopant redistribution. Furthermore, the quality factor (I-ON/S.S.) of the VC-JLT is also benchmarked with recently published poly-Si JLTs, showing that the proposed VC-JLT exhibits good S.S. and a record I-ON , which makes it as a promising device for 3-D integrated nanoelectronics.